`pyuvm._reg.uvm_reg_model`

Module Contents

Data

`__all__`
`UVM_DEFAULT_PATH`
`UVM_REG_DATA_WIDTH`

API

pyuvm._reg.uvm_reg_model.__all__: [‘UVM_DEFAULT_PATH’, ‘UVM_REG_DATA_WIDTH’, ‘uvm_reg_data_t’, ‘uvm_reg_data_logic_t’, ‘uvm_reg_addr_t…

class pyuvm._reg.uvm_reg_model.uvm_reg_data_t: Bases: int

class pyuvm._reg.uvm_reg_model.uvm_reg_data_logic_t: Bases: int

class pyuvm._reg.uvm_reg_model.uvm_reg_addr_t: Bases: int

class pyuvm._reg.uvm_reg_model.uvm_reg_addr_logic_t: Bases: int

class pyuvm._reg.uvm_reg_model.uvm_reg_byte_en_t: Bases: int

class pyuvm._reg.uvm_reg_model.uvm_reg_cvr_t: Bases: int

class pyuvm._reg.uvm_reg_model.uvm_hdl_path_slice(name='')

Bases: pyuvm._s05_base_classes.uvm_object

path: str: None

offset: int: None

size: int: None

class pyuvm._reg.uvm_reg_model.uvm_status_e(*args, **kwds)

Bases: enum.Enum

UVM_IS_OK: 0

UVM_NOT_OK: 1

UVM_HAS_X: 2

class pyuvm._reg.uvm_reg_model.uvm_door_e(*args, **kwds)

Bases: enum.Enum

UVM_FRONTDOOR: 0

UVM_BACKDOOR: 1

UVM_PREDICT: 2

UVM_DEFAULT_DOOR: 3

class pyuvm._reg.uvm_reg_model.uvm_path_e(*args, **kwds): Bases: enum.Enum

class pyuvm._reg.uvm_reg_model.uvm_check_e(*args, **kwds)

Bases: enum.Enum

UVM_NO_CHECK: 0

UVM_CHECK: 1

class pyuvm._reg.uvm_reg_model.uvm_endianness_e(*args, **kwds)

Bases: enum.Enum

UVM_NO_ENDIAN: 0

UVM_LITTLE_ENDIAN: 1

UVM_BIG_ENDIAN: 2

UVM_LITTLE_FIFO: 3

UVM_BIG_FIFO: 4

class pyuvm._reg.uvm_reg_model.uvm_elem_kind_e(*args, **kwds)

Bases: enum.Enum

UVM_REG: 0

UVM_FIELD: 1

UVM_MEM: 2

class pyuvm._reg.uvm_reg_model.uvm_access_e(*args, **kwds)

Bases: enum.Enum

UVM_READ: 0

UVM_WRITE: 1

UVM_BURST_READ: 2

UVM_BURST_WRITE: 3

class pyuvm._reg.uvm_reg_model.uvm_hier_e(*args, **kwds)

Bases: enum.Enum

UVM_NO_HIER: 0

UVM_HIER: 1

class pyuvm._reg.uvm_reg_model.uvm_predict_e(*args, **kwds)

Bases: enum.Enum

UVM_PREDICT_DIRECT: 0

UVM_PREDICT_READ: 1

UVM_PREDICT_WRITE: 2

class pyuvm._reg.uvm_reg_model.uvm_coverage_model_e(*args, **kwds)

Bases: enum.Enum

UVM_NO_COVERAGE: 0

UVM_CVR_REG_BITS: 1

UVM_CVR_ADDR_MAP: 2

UVM_CVR_FIELD_VALS: 4

UVM_CVR_ALL: None

class pyuvm._reg.uvm_reg_model.uvm_reg_mem_test_e

Bases: enum.IntEnum

UVM_DO_REG_HW_RESET: 1

UVM_DO_REG_BIT_BASH: 2

UVM_DO_REG_ACCESS: 4

UVM_DO_MEM_ACCESS: 8

UVM_DO_SHARED_ACCESS: 16

UVM_DO_MEM_WALK: 32

UVM_DO_ALL_REG_MEM_TESTS: 18446744073709551615

class pyuvm._reg.uvm_reg_model.uvm_hdl_path_concat(name: str = ''): Bases: pyuvm._s05_base_classes.uvm_object

class pyuvm._reg.uvm_reg_model.uvm_reg_backdoor(name: str = ''): Bases: pyuvm._s05_base_classes.uvm_object

class pyuvm._reg.uvm_reg_model.uvm_reg_frontdoor: Initialization

class pyuvm._reg.uvm_reg_model.uvm_reg_map_addr_range: Initialization

class pyuvm._reg.uvm_reg_model.uvm_object_string_pool(name: str = ''): Bases: pyuvm._s05_base_classes.uvm_object

pyuvm._reg.uvm_reg_model.UVM_DEFAULT_PATH: pyuvm._reg.uvm_reg_model.uvm_door_e: None

pyuvm._reg.uvm_reg_model.UVM_REG_DATA_WIDTH: int: 64

`uvm_reg_data_t`
`uvm_reg_data_logic_t`
`uvm_reg_addr_t`
`uvm_reg_addr_logic_t`
`uvm_reg_byte_en_t`
`uvm_reg_cvr_t`
`uvm_hdl_path_slice`
`uvm_status_e`
`uvm_door_e`
`uvm_path_e`
`uvm_check_e`
`uvm_endianness_e`
`uvm_elem_kind_e`
`uvm_access_e`
`uvm_hier_e`
`uvm_predict_e`
`uvm_coverage_model_e`
`uvm_reg_mem_test_e`
`uvm_hdl_path_concat`
`uvm_reg_backdoor`
`uvm_reg_frontdoor`
`uvm_reg_map_addr_range`
`uvm_object_string_pool`

pyuvm._reg.uvm_reg_model

Module Contents

Classes

Data

API

`pyuvm._reg.uvm_reg_model`