`pyuvm._s12_uvm_tlm_interfaces`

Module Contents

Classes

`uvm_export_base`
`uvm_port_base`	A `uvm_port_base` is a uvm_component with a `connect()` function. The `connect` function creates an `__export` data member that implements the put/get,etc methods.
`uvm_blocking_put_port`	Access the blocking put interfaces
`uvm_nonblocking_put_port`	Access the non_blocking put interface
`uvm_put_port`
`uvm_blocking_get_port`	Access the blocking get export methods
`uvm_nonblocking_get_port`	Access the non_blocking methods in export
`uvm_get_port`
`uvm_blocking_peek_port`	Provides access to the peek methods
`uvm_nonblocking_peek_port`	Try a peek
`uvm_peek_port`
`uvm_blocking_get_peek_port`
`uvm_nonblocking_get_peek_port`
`uvm_get_peek_port`
`uvm_blocking_transport_port`
`uvm_nonblocking_transport_port`
`uvm_transport_port`
`uvm_blocking_master_port`
`uvm_nonblocking_master_port`
`uvm_master_port`
`uvm_blocking_slave_port`
`uvm_nonblocking_slave_port`
`uvm_slave_port`
`uvm_analysis_imp`
`uvm_analysis_port`
`uvm_nonblocking_put_export`
`uvm_blocking_put_export`
`uvm_put_export`
`uvm_nonblocking_get_export`
`uvm_blocking_get_export`
`uvm_get_export`
`uvm_nonblocking_peek_export`
`uvm_blocking_peek_export`
`uvm_peek_export`
`uvm_blocking_get_peek_export`
`uvm_nonblocking_get_peek_export`
`uvm_get_peek_export`
`uvm_blocking_transport_export`
`uvm_nonblocking_transport_export`
`uvm_transport_export`
`uvm_blocking_master_export`
`uvm_nonblocking_master_export`
`uvm_master_export`
`uvm_blocking_slave_export`
`uvm_nonblocking_slave_export`
`uvm_slave_export`
`uvm_analysis_export`
`uvm_QueueAccessor`
`uvm_tlm_fifo_base`	Declares and instantiate the exports needed to communicate through the Queue.
`uvm_tlm_fifo`
`uvm_tlm_analysis_fifo`
`uvm_tlm_req_rsp_channel`
`uvm_tlm_transport_channel`

API

class pyuvm._s12_uvm_tlm_interfaces.uvm_export_base(name, parent): Bases: pyuvm._s13_uvm_component.uvm_component

class pyuvm._s12_uvm_tlm_interfaces.uvm_port_base(name, parent)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_export_base

A uvm_port_base is a uvm_component with a connect() function. The connect function creates an __export data member that implements the put/get,etc methods.

We’ll build functionality from uvm_port_base to create the other combinations of ports through multiple inheritance.

pyuvm will make extensive use of Pythons “ask forgiveness” policy If you try to use the wrong method for the port you created then you’ll get a exception, maybe a missing attribute exception, though we could catch that one and deliver a more useful message.

Unlike the SV implementation of UVM we return results from get and peek as function call returns. This is more pythonic.

Initialization

13.1.2.1—This is new() in the IEEE-UVM, but we mean the same thing with init()

:param name: The name of the component. Used in the UVM hierarchy :param parent: The parent component. If None, the parent is uvm_root

__tlm_method_list: [‘put’, ‘get’, ‘peek’, ‘try_put’, ‘try_get’, ‘try_peek’, ‘can_put’, ‘can_get’, ‘can_peek’, ‘transpor…

_check_export(export): Check that the export implements needed methods

connect(export)

:param export: The export that has the functions :raises: UVMTLMConnectionError if there is a connect error :return: None

Attach this port to the associated export.

class pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_put_port(name, parent)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_port_base

Access the blocking put interfaces

Initialization

13.1.2.1—This is new() in the IEEE-UVM, but we mean the same thing with init()

:param name: The name of the component. Used in the UVM hierarchy :param parent: The parent component. If None, the parent is uvm_root

async put(datum)

:param datum: Datum to put
:raises: UVMTLMConnectionError if export is missing
:return: None

put the datum

class pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_put_port(name, parent)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_port_base

Access the non_blocking put interface

Initialization

13.1.2.1—This is new() in the IEEE-UVM, but we mean the same thing with init()

:param name: The name of the component. Used in the UVM hierarchy :param parent: The parent component. If None, the parent is uvm_root

try_put(data)

:param data: data to deliver :raises: UVMTLMConnectionError if export is missing :return: boolean True = success

Tries to put data on a port, but if the port is full it returns False

can_put()

Returns true if there is room for data to be put on the port

:return: True if there is room to put

class pyuvm._s12_uvm_tlm_interfaces.uvm_put_port(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_put_port, pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_put_port

class pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_get_port(name, parent)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_port_base

Access the blocking get export methods

Initialization

13.1.2.1—This is new() in the IEEE-UVM, but we mean the same thing with init()

:param name: The name of the component. Used in the UVM hierarchy :param parent: The parent component. If None, the parent is uvm_root

async get()

:raises: UVMTLMConnectionError if export is missing :return: data

A blocking get that returns the data got

class pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_get_port(name, parent)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_port_base

Access the non_blocking methods in export

Initialization

13.1.2.1—This is new() in the IEEE-UVM, but we mean the same thing with init()

:param name: The name of the component. Used in the UVM hierarchy :param parent: The parent component. If None, the parent is uvm_root

try_get()

:raises: UVMTLMConnectionError if export is missing :return: (success, data)

12.2.4.2.6 Returns a tuple containing success and the data This is different than SV UVM that returns the data through the argument list. :return: (success, data)

can_get(): :raises: UVMTLMConnectionError if export is missing :return: bool Returns true if there is data to get

class pyuvm._s12_uvm_tlm_interfaces.uvm_get_port(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_get_port, pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_get_port

class pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_peek_port(name, parent)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_port_base

Provides access to the peek methods

Initialization

13.1.2.1—This is new() in the IEEE-UVM, but we mean the same thing with init()

:param name: The name of the component. Used in the UVM hierarchy :param parent: The parent component. If None, the parent is uvm_root

async peek()

:raises: UVMTLMConnectionError if export is missing :return: datum

A blocking peek that returns data without consuming it.

class pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_peek_port(name, parent)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_port_base

Try a peek

Initialization

13.1.2.1—This is new() in the IEEE-UVM, but we mean the same thing with init()

:param name: The name of the component. Used in the UVM hierarchy :param parent: The parent component. If None, the parent is uvm_root

try_peek()

:raises: UVMTLMConnectionError if export is missing :return: (success, data)

Tries to peek for data and returns a tuple with success and the data

can_peek()

:raises: UVMTLMConnectionError if export is missing :return: True if can peek

Checks if peeking will be successful

class pyuvm._s12_uvm_tlm_interfaces.uvm_peek_port(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_peek_port, pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_peek_port

class pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_get_peek_port(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_get_port, pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_peek_port

class pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_get_peek_port(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_get_port, pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_peek_port

class pyuvm._s12_uvm_tlm_interfaces.uvm_get_peek_port(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_get_peek_port, pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_get_peek_port

class pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_transport_port(name, parent)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_port_base

async transport(put_data)

Puts data and blocks if there is no room, then blocks if there is no data to get and gets data.

:param put_data: data to send :raises: UVMTLMConnectionError if export is missing :return: data received

class pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_transport_port(name, parent)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_port_base

nb_transport(put_data)

Non-blocking transport. Returns a tuple with success if the transport was successful and the data could be returned

:param put_data: data to send :raises: UVMTLMConnectionError if export is missing :return: (success, data)

class pyuvm._s12_uvm_tlm_interfaces.uvm_transport_port(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_transport_port, pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_transport_port

class pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_master_port(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_put_port, pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_get_peek_port

class pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_master_port(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_put_port, pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_get_peek_port

class pyuvm._s12_uvm_tlm_interfaces.uvm_master_port(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_master_port, pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_master_port

class pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_slave_port(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_put_port, pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_get_peek_port

class pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_slave_port(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_get_peek_port, pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_put_port

class pyuvm._s12_uvm_tlm_interfaces.uvm_slave_port(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_slave_port, pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_slave_port

class pyuvm._s12_uvm_tlm_interfaces.uvm_analysis_imp(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_port_base

class pyuvm._s12_uvm_tlm_interfaces.uvm_analysis_port(name, parent)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_port_base

write(datum)

Write to all connected analysis ports. This is a broadcast. Returns regardless of whether there are any subscribers.

:param datum: data to send :raises: UVMTLMConnectionError if export is missing :return: None

connect(export)

class pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_put_export(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_export_base

class pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_put_export(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_export_base

class pyuvm._s12_uvm_tlm_interfaces.uvm_put_export(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_put_export, pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_put_export

class pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_get_export(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_export_base

class pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_get_export(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_export_base

class pyuvm._s12_uvm_tlm_interfaces.uvm_get_export(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_get_export, pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_get_export

class pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_peek_export(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_export_base

class pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_peek_export(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_export_base

class pyuvm._s12_uvm_tlm_interfaces.uvm_peek_export(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_peek_export, pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_peek_export

class pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_get_peek_export(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_export_base

class pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_get_peek_export(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_export_base

class pyuvm._s12_uvm_tlm_interfaces.uvm_get_peek_export(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_get_peek_export, pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_get_peek_export

class pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_transport_export(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_export_base

class pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_transport_export(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_export_base

class pyuvm._s12_uvm_tlm_interfaces.uvm_transport_export(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_transport_export, pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_transport_export

class pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_master_export(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_put_export, pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_get_peek_export

class pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_master_export(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_peek_export, pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_get_peek_export

class pyuvm._s12_uvm_tlm_interfaces.uvm_master_export(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_master_export, pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_master_export

class pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_slave_export(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_put_export, pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_get_peek_export

class pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_slave_export(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_put_export, pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_get_peek_export

class pyuvm._s12_uvm_tlm_interfaces.uvm_slave_export(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_slave_export, pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_slave_export

class pyuvm._s12_uvm_tlm_interfaces.uvm_analysis_export(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_export_base

class pyuvm._s12_uvm_tlm_interfaces.uvm_QueueAccessor(name, parent, uvm_queue, ap): Initialization

class pyuvm._s12_uvm_tlm_interfaces.uvm_tlm_fifo_base(name, parent, maxsize=1)

Bases: pyuvm._s13_uvm_component.uvm_component

Declares and instantiate the exports needed to communicate through the Queue.

Initialization

13.1.2.1—This is new() in the IEEE-UVM, but we mean the same thing with init()

:param name: The name of the component. Used in the UVM hierarchy :param parent: The parent component. If None, the parent is uvm_root

class uvm_BlockingPutExport(name, parent, uvm_queue, ap)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_QueueAccessor, pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_put_export

async put(item)

:param item: item to put :return: None

A coroutine that blocks if the FIFO is full.

class uvm_NonBlockingPutExport(name, parent, uvm_queue, ap)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_QueueAccessor, pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_put_export

can_put(): :return: True if can put

try_put(item)

:param item: item to put :raises: QueueFull if the queue is full :return: True if successful

The try_put is implemented with an exception rather than returning a boolean.

class uvm_PutExport(name, parent, uvm_queue, ap): Bases: uvm_BlockingPutExport, uvm_NonBlockingPutExport

class uvm_BlockingGetExport(name, parent, uvm_queue, ap)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_QueueAccessor, pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_get_export

async get()

:return: item

A coroutine that blocks if the FIFO is empty

class uvm_NonBlockingGetExport(name, parent, uvm_queue, ap)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_QueueAccessor, pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_get_export

can_get(): :return: True if can get

try_get(): :return: (success, item)

class uvm_GetExport(name, parent, uvm_queue, ap): Bases: uvm_BlockingGetExport, uvm_NonBlockingGetExport

class uvm_BlockingPeekExport(name, parent, uvm_queue, ap)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_QueueAccessor, pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_peek_export

async peek()

:return: item

A coroutine that blocks if the FIFO is empty

class uvm_NonBlockingPeekExport(name, parent, uvm_queue, ap)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_QueueAccessor, pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_peek_export

can_peek(): :return: True if can peek

try_peek(): :return: (success, item)

class uvm_PeekExport(name, parent, uvm_queue, ap): Bases: uvm_BlockingPeekExport, uvm_NonBlockingPeekExport

class uvm_BlockingGetPeekExport(name, parent, uvm_queue, ap): Bases: uvm_BlockingGetExport, uvm_BlockingPeekExport

class uvm_NonBlockingGetPeekExport(name, parent, uvm_queue, ap): Bases: uvm_NonBlockingGetExport, uvm_NonBlockingPeekExport

class uvm_GetPeekExport(name, parent, uvm_queue, ap): Bases: uvm_GetExport, uvm_PeekExport

async put(item)

:param item: item to put

Blocking put coroutine

can_put(): :return: True if can put

try_put(item): :param item: item to put :return: True if successful

async get()

:return: item

coroutine that blocks if FIFO is empty

can_get(): :return: True if can get

try_get(): :return: (success, item)

async peek()

:return: item

A coroutine that blocks if FIFO is empty

can_peek(): :return: True if can peek

try_peek(): :return: (success, item)

class pyuvm._s12_uvm_tlm_interfaces.uvm_tlm_fifo(name=None, parent=None, size=1)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_tlm_fifo_base

size()

:return: size of FIFO

Return the size of the fifo

used()

:return: Number of items in the FIFO

How much of the FIFO is being used?

is_empty()

Returns true if FIFO is empty

:return: True if empty

is_full()

Test for full FIFO

:return: True if full

flush(): Flush out the FIFO

class pyuvm._s12_uvm_tlm_interfaces.uvm_tlm_analysis_fifo(name, parent=None)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_tlm_fifo

class uvm_AnalysisExport(name, parent, uvm_queue, ap)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_QueueAccessor, pyuvm._s12_uvm_tlm_interfaces.uvm_analysis_port

write(item)

:param item: item to write

Writes the item to all the subscribers, or no one if there are no subscribers.

class pyuvm._s12_uvm_tlm_interfaces.uvm_tlm_req_rsp_channel(name, parent=None, request_fifo_size=1, response_fifo_size=1)

Bases: pyuvm._s13_uvm_component.uvm_component

class uvm_MasterSlaveExport(name, parent, put_export, get_peek_export)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_master_port, pyuvm._s12_uvm_tlm_interfaces.uvm_get_peek_port

async put(item)

:param item: item to put

A coroutine that blocks if the FIFO is full

can_put(): :return: True if can put

try_put(item): :param item: item to put :return: True if successful

async get()

:return: item

A coroutine that blocks if the FIFO is empty

can_get(): :return: True if can get

try_get(): :return: (success, item)

connect_phase()

class pyuvm._s12_uvm_tlm_interfaces.uvm_tlm_transport_channel(name, parent=None)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_tlm_req_rsp_channel

class uvm_TransportExport(name, parent, req_fifo, rsp_fifo)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_transport_port

async transport(req)

nb_transport(req)

pyuvm._s12_uvm_tlm_interfaces

Module Contents

Classes

API

`pyuvm._s12_uvm_tlm_interfaces`