pyuvm 

For methods that we haven’t yet implemented.

Initialization

Initialize self. See help(type(self)) for accurate signature.

exception pyuvm.UsePythonMethod

For cases where the user should use a Python method rather than a UVM method.

Initialization

Initialize self. See help(type(self)) for accurate signature.

exception pyuvm.UVMFactoryError

For cases where a type is not registered with the factory

Initialization

Initialize self. See help(type(self)) for accurate signature.

exception pyuvm.UVMTLMConnectionError

For problems connecting TLM

Initialization

Initialize self. See help(type(self)) for accurate signature.

exception pyuvm.UVMBadPhase

Errors in phasing

Initialization

Initialize self. See help(type(self)) for accurate signature.

exception pyuvm.UVMSequenceError

Errors using sequences

Initialization

Initialize self. See help(type(self)) for accurate signature.

exception pyuvm.UVMConfigError

Errors using the config_db

Initialization

Initialize self. See help(type(self)) for accurate signature.

exception pyuvm.UVMConfigItemNotFound

Couldn’t find something in config_db

Initialization

Initialize self. See help(type(self)) for accurate signature.

exception pyuvm.UVMFatalError

Used to dump out of the testbench

Initialization

Initialize self. See help(type(self)) for accurate signature.

pyuvm.test(timeout_time=None, timeout_unit='step', expect_fail=False, expect_error=(), skip=False, stage=None, keep_singletons=False, keep_set=set())

class pyuvm.uvm_mem(name: str, size: int, n_bits: int, access: str = 'RW', has_coverage: int = uvm_coverage_model_e.UVM_NO_COVERAGE)

_max_size: ClassVar[int]: 0

configure(parent: pyuvm._reg.uvm_reg_block.uvm_reg_block, hdl_path: str = '') → None

set_offset(map: pyuvm._reg.uvm_reg_map.uvm_reg_map, offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, unmapped: bool = False) → None

set_parent(parent: pyuvm._reg.uvm_reg_block.uvm_reg_block) → None

add_map(map: pyuvm._reg.uvm_reg_map.uvm_reg_map) → None

_lock_model() → None

abstractmethod _add_vreg(vreg: pyuvm._reg.uvm_vreg.uvm_vreg) → None

abstractmethod _delete_vreg(vreg: pyuvm._reg.uvm_vreg.uvm_vreg) → None

get_full_name() → str

get_parent() → pyuvm._reg.uvm_reg_block.uvm_reg_block

get_block() → pyuvm._reg.uvm_reg_block.uvm_reg_block

get_n_maps() → int

is_in_map(map: pyuvm._reg.uvm_reg_map.uvm_reg_map) → bool

get_maps(maps: list[pyuvm._reg.uvm_reg_map.uvm_reg_map]) → None

get_local_map(map: pyuvm._reg.uvm_reg_map.uvm_reg_map) → pyuvm._reg.uvm_reg_map.uvm_reg_map | None

get_default_map() → pyuvm._reg.uvm_reg_map.uvm_reg_map | None

get_rights(map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None) → str

get_access(map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None) → str

get_size() → int

get_n_bytes() → int

get_n_bits() → int

static get_max_size() → int

get_virtual_registers() → list[pyuvm._reg.uvm_vreg.uvm_vreg]

get_virtual_fields() → list[pyuvm._reg.uvm_vreg_field.uvm_vreg_field]

abstractmethod get_vreg(name: str) → pyuvm._reg.uvm_vreg.uvm_vreg

get_vreg_by_name(name: str) → pyuvm._reg.uvm_vreg.uvm_vreg | None

get_vfield_by_name(name: str) → pyuvm._reg.uvm_vreg_field.uvm_vreg_field | None

abstractmethod get_vreg_by_offset(offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None) → pyuvm._reg.uvm_vreg.uvm_vreg

abstractmethod get_offset(offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t = 0, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None) → pyuvm._reg.uvm_reg_model.uvm_reg_addr_t

get_address(offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t = 0, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None) → pyuvm._reg.uvm_reg_model.uvm_reg_addr_t

get_addresses(offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t = 0, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None) → tuple[int, list[pyuvm._reg.uvm_reg_model.uvm_reg_addr_t]]

abstractmethod async write(offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, value: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_DEFAULT_DOOR, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, prior: int = -1, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → pyuvm._reg.uvm_reg_model.uvm_status_e

abstractmethod async read(offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_DEFAULT_DOOR, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, prior: int = -1, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → tuple[pyuvm._reg.uvm_reg_model.uvm_status_e, pyuvm._reg.uvm_reg_model.uvm_reg_data_t]

abstractmethod async burst_write(offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, value: list[pyuvm._reg.uvm_reg_model.uvm_reg_data_t], path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_DEFAULT_DOOR, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, prior: int = -1, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → pyuvm._reg.uvm_reg_model.uvm_status_e

abstractmethod async burst_read(offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, value: list[pyuvm._reg.uvm_reg_model.uvm_reg_data_t], path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_DEFAULT_DOOR, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, prior: int = -1, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → pyuvm._reg.uvm_reg_model.uvm_status_e

abstractmethod async poke(offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, value: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, kind: str = '', parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → pyuvm._reg.uvm_reg_model.uvm_status_e

abstractmethod async peek(offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, kind: str = '', parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → tuple[pyuvm._reg.uvm_reg_model.uvm_status_e, pyuvm._reg.uvm_reg_model.uvm_reg_data_t]

abstractmethod _check_access(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → pyuvm._reg.uvm_reg_map.uvm_reg_map_info | None

abstractmethod async do_write(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

abstractmethod async do_read(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

abstractmethod set_frontdoor(ftdr: pyuvm._reg.uvm_reg_sequence.uvm_reg_frontdoor, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, fname: str = '', lineno: int = 0) → None

abstractmethod get_frontdoor(map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None) → pyuvm._reg.uvm_reg_sequence.uvm_reg_frontdoor

abstractmethod set_backdoor(bkdr: pyuvm._reg.uvm_reg_backdoor.uvm_reg_backdoor, fname: str = '', lineno: int = 0) → None

abstractmethod get_backdoor(inherited: bool = True) → pyuvm._reg.uvm_reg_backdoor.uvm_reg_backdoor

abstractmethod clear_hdl_path(kind: str = 'RTL') → None

abstractmethod add_hdl_path(slices: list[pyuvm._reg.uvm_reg_model.uvm_hdl_path_slice], kind: str = 'RTL') → None

abstractmethod add_hdl_path_slice(name: str, offset: int, size: int, first: bool = False, kind: str = 'RTL') → None

abstractmethod has_hdl_path(kind: str = '') → bool

abstractmethod get_hdl_path(paths: list[pyuvm._reg.uvm_reg_model.uvm_hdl_path_concat], kind: str = '') → None

abstractmethod get_full_hdl_path(paths: list[pyuvm._reg.uvm_reg_model.uvm_hdl_path_concat], kind: str = '', separator: str = '.') → None

abstractmethod get_hdl_path_kinds(kinds: list[str]) → None

abstractmethod async backdoor_read(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

abstractmethod async backdoor_write(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

abstractmethod backdoor_read_func(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → pyuvm._reg.uvm_reg_model.uvm_status_e

abstractmethod async pre_write(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

abstractmethod async post_write(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

abstractmethod async pre_read(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

abstractmethod async post_read(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

abstractmethod build_coverage(models: pyuvm._reg.uvm_reg_model.uvm_reg_cvr_t) → pyuvm._reg.uvm_reg_model.uvm_reg_cvr_t

abstractmethod add_coverage(models: pyuvm._reg.uvm_reg_model.uvm_reg_cvr_t) → None

abstractmethod set_coverage(is_on: pyuvm._reg.uvm_reg_model.uvm_reg_cvr_t) → pyuvm._reg.uvm_reg_model.uvm_reg_cvr_t

abstractmethod get_coverage(is_on: pyuvm._reg.uvm_reg_model.uvm_reg_cvr_t) → bool

abstractmethod sample(offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, is_read: bool, map: pyuvm._reg.uvm_reg_map.uvm_reg_map) → None

_sample(addr: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, is_read: bool, map: pyuvm._reg.uvm_reg_map.uvm_reg_map) → None

class pyuvm.uvm_mem_mam_cfg

n_bytes: int: None

start_offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t: None

end_offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t: None

mode: alloc_mode_e: None

locality: locality_e: None

class pyuvm.uvm_mem_mam(name: str, cfg: pyuvm._reg.uvm_mem_mam.uvm_mem_mam_cfg, mem: pyuvm._reg.uvm_mem.uvm_mem = None)

abstractmethod reconfigure(cfg: pyuvm._reg.uvm_mem_mam.uvm_mem_mam_cfg = None) → pyuvm._reg.uvm_mem_mam.uvm_mem_mam_cfg

abstractmethod reserve_region(start_offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, n_bytes: int, fname: str = '', lineno: int = 0) → pyuvm._reg.uvm_mem_mam.uvm_mem_region

abstractmethod request_region(n_bytes: int, alloc: pyuvm._reg.uvm_mem_mam.uvm_mem_mam_policy = None, fname: str = '', lineno: int = 0) → pyuvm._reg.uvm_mem_mam.uvm_mem_region

abstractmethod release_region(region: pyuvm._reg.uvm_mem_mam.uvm_mem_region) → None

abstractmethod release_all_regions() → None

abstractmethod for_each() → pyuvm._reg.uvm_mem_mam.uvm_mem_region

abstractmethod get_memory() → pyuvm._reg.uvm_mem.uvm_mem

class pyuvm.uvm_mem_region(start_offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, end_offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, len: int, n_bytes: int, parent: pyuvm._reg.uvm_mem_mam.uvm_mem_mam)

abstractmethod get_start_offset() → pyuvm._reg.uvm_reg_model.uvm_reg_addr_t

abstractmethod get_end_offset() → pyuvm._reg.uvm_reg_model.uvm_reg_addr_t

abstractmethod get_len() → int

abstractmethod get_n_bytes() → int

abstractmethod release_region() → None

abstractmethod get_memory() → pyuvm._reg.uvm_mem.uvm_mem

abstractmethod get_virtual_registers() → pyuvm._reg.uvm_vreg.uvm_vreg

abstractmethod async write(offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, value: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_DEFAULT_DOOR, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, prior: int = -1, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → pyuvm._reg.uvm_reg_model.uvm_status_e

abstractmethod async read(offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_DEFAULT_DOOR, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, prior: int = -1, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → tuple[pyuvm._reg.uvm_reg_model.uvm_status_e, pyuvm._reg.uvm_reg_model.uvm_reg_data_t]

abstractmethod async burst_write(offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, value: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_DEFAULT_DOOR, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, prior: int = -1, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → pyuvm._reg.uvm_reg_model.uvm_status_e

abstractmethod async burst_read(offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_DEFAULT_DOOR, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, prior: int = -1, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → tuple[pyuvm._reg.uvm_reg_model.uvm_status_e, list[pyuvm._reg.uvm_reg_model.uvm_reg_data_t]]

abstractmethod async poke(offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, value: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → pyuvm._reg.uvm_reg_model.uvm_status_e

abstractmethod async peek(offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → tuple[pyuvm._reg.uvm_reg_model.uvm_status_e, pyuvm._reg.uvm_reg_model.uvm_reg_data_t]

class pyuvm.uvm_mem_mam_policy

len: int: None

start_offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t: None

min_offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t: None

max_offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t: None

in_use: list[pyuvm._reg.uvm_mem_mam.uvm_mem_region]: None

class pyuvm.uvm_reg(name='', n_bits: int = 0, has_coverage: int = 0, **kwargs)

_max_size: ClassVar[int]: 0

_reg_registry: ClassVar[dict[str, pyuvm._reg.uvm_reg.uvm_reg]]: None

configure(blk_parent: pyuvm._reg.uvm_reg_block.uvm_reg_block, regfile_parent: pyuvm._reg.uvm_reg_file.uvm_reg_file = None, hdl_path: str = '', throw_error_on_read: bool = False, throw_error_on_write: bool = False, **kwargs) → None

set_offset(map: pyuvm._reg.uvm_reg_map.uvm_reg_map, offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, unmapped: bool = False) → None

abstractmethod _set_parent(blk_parent: pyuvm._reg.uvm_reg_block.uvm_reg_block, regfile_parent: pyuvm._reg.uvm_reg_file.uvm_reg_file) → None

_add_field(field: pyuvm._reg.uvm_reg_field.uvm_reg_field) → None

add_map(map: pyuvm._reg.uvm_reg_map.uvm_reg_map) → None

_lock_model() → None

_unlock_model() → None

abstractmethod unregister(map: pyuvm._reg.uvm_reg_map.uvm_reg_map) → None

get_full_name() → str

get_parent() → pyuvm._reg.uvm_reg_block.uvm_reg_block

get_block() → pyuvm._reg.uvm_reg_block.uvm_reg_block

get_regfile() → pyuvm._reg.uvm_reg_file.uvm_reg_file

get_n_maps() → int

is_in_map(map: pyuvm._reg.uvm_reg_map.uvm_reg_map) → bool

get_maps(maps: list[pyuvm._reg.uvm_reg_map.uvm_reg_map]) → None

get_local_map(map: pyuvm._reg.uvm_reg_map.uvm_reg_map) → pyuvm._reg.uvm_reg_map.uvm_reg_map | None

get_default_map() → pyuvm._reg.uvm_reg_map.uvm_reg_map | None

get_rights(map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None) → str

get_n_bits() → int

get_n_bytes() → int

static get_max_size() → int

get_fields() → list[pyuvm._reg.uvm_reg_field.uvm_reg_field]

abstractmethod get_field_by_name(name: str) → pyuvm._reg.uvm_reg_field.uvm_reg_field

_get_fields_access(map: pyuvm._reg.uvm_reg_map.uvm_reg_map) → str

abstractmethod get_offset(map: pyuvm._reg.uvm_reg_map.uvm_reg_map) → pyuvm._reg.uvm_reg_model.uvm_reg_addr_t

get_address(map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None) → pyuvm._reg.uvm_reg_model.uvm_reg_addr_t

get_addresses(map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None) → tuple[int, list[pyuvm._reg.uvm_reg_model.uvm_reg_addr_t]]

static get_reg_by_full_name(full_name: str) → pyuvm._reg.uvm_reg.uvm_reg | None

set(value: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, fname: str = '', lineno: int = 0) → None

get(fname: str = '', lineno: int = 0) → pyuvm._reg.uvm_reg_model.uvm_reg_data_t

get_mirrored_value(fname: str = '', lineno: int = 0) → int

abstractmethod needs_update() → bool

reset(kind: str = 'HARD') → None

abstractmethod get_reset(kind: str = 'HARD') → int

abstractmethod has_reset(kind: str = 'HARD', delete: bool = False) → bool

abstractmethod set_reset(value: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, kind: str = 'HARD') → None

async write(value: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_DEFAULT_DOOR, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, prior: int = -1, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0, **kwargs) → pyuvm._reg.uvm_reg_model.uvm_status_e

async read(path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_DEFAULT_DOOR, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, prior: int = -1, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0, **kwargs) → tuple[pyuvm._reg.uvm_reg_model.uvm_status_e, pyuvm._reg.uvm_reg_model.uvm_reg_data_t]

abstractmethod async poke(value: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, kind: str = '', parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → pyuvm._reg.uvm_reg_model.uvm_status_e

abstractmethod async peek(kind: str = '', parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → tuple[pyuvm._reg.uvm_reg_model.uvm_status_e, pyuvm._reg.uvm_reg_model.uvm_reg_data_t]

abstractmethod async update(path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_DEFAULT_DOOR, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, prior: int = -1, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → pyuvm._reg.uvm_reg_model.uvm_status_e

abstractmethod async mirror(check: pyuvm._reg.uvm_reg_model.uvm_check_e = uvm_check_e.UVM_NO_CHECK, path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_DEFAULT_DOOR, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, prior: int = -1, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → pyuvm._reg.uvm_reg_model.uvm_status_e

predict(value: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, be: pyuvm._reg.uvm_reg_model.uvm_reg_byte_en_t = -1, kind: pyuvm._reg.uvm_reg_model.uvm_predict_e = uvm_predict_e.UVM_PREDICT_DIRECT, path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_FRONTDOOR, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, fname: str = '', lineno: int = 0) → bool

is_busy() → bool

_set_is_busy(busy: bool) → None

async _read(path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_DEFAULT_DOOR, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, prior: int = -1, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → tuple[pyuvm._reg.uvm_reg_model.uvm_status_e, pyuvm._reg.uvm_reg_model.uvm_reg_data_t]

_check_access(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → tuple[bool, pyuvm._reg.uvm_reg_map.uvm_reg_map_info | None]

abstractmethod do_check(expected: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, actual: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, map: pyuvm._reg.uvm_reg_map.uvm_reg_map) → bool

async do_write(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

abstractmethod async _do_write_backdoor(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item, map_info: pyuvm._reg.uvm_reg_map.uvm_reg_map_info) → None

async _do_write_frontdoor(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item, map_info: pyuvm._reg.uvm_reg_map.uvm_reg_map_info) → None

async do_read(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

abstractmethod async _do_read_backdoor(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item, map_info: pyuvm._reg.uvm_reg_map.uvm_reg_map_info) → None

async _do_read_frontdoor(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item, map_info: pyuvm._reg.uvm_reg_map.uvm_reg_map_info) → None

do_predict(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item, kind: pyuvm._reg.uvm_reg_model.uvm_predict_e, be: pyuvm._reg.uvm_reg_model.uvm_reg_byte_en_t = -1) → None

abstractmethod set_frontdoor(ftdr: pyuvm._reg.uvm_reg_sequence.uvm_reg_frontdoor, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, fname: str = '', lineno: int = 0) → None

abstractmethod get_frontdoor(map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None) → pyuvm._reg.uvm_reg_sequence.uvm_reg_frontdoor

abstractmethod set_backdoor(bkdr: pyuvm._reg.uvm_reg_backdoor.uvm_reg_backdoor, fname: str = '', lineno: int = 0) → None

abstractmethod get_backdoor(inherited: bool = True) → pyuvm._reg.uvm_reg_backdoor.uvm_reg_backdoor

abstractmethod clear_hdl_path(kind: str = 'RTL') → None

abstractmethod add_hdl_path(slices: list[pyuvm._reg.uvm_reg_model.uvm_hdl_path_slice], kind: str = 'RTL') → None

add_hdl_path_slice(name: str, offset: int, size: int, first: bool = False, kind: str = 'RTL') → None

abstractmethod has_hdl_path(kind: str = '') → bool

abstractmethod get_hdl_path(paths: list[pyuvm._reg.uvm_reg_model.uvm_hdl_path_concat], kind: str = '') → None

abstractmethod get_hdl_path_kind(kinds: list[str]) → None

abstractmethod get_full_hdl_path(paths: list[pyuvm._reg.uvm_reg_model.uvm_hdl_path_concat], kind: str = '', separator: str = '.') → None

abstractmethod async backdoor_read(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

abstractmethod async backdoor_write(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

abstractmethod backdoor_read_func(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → pyuvm._reg.uvm_reg_model.uvm_status_e

abstractmethod backdoor_watch() → None

abstractmethod include_coverage(scope: str, models: pyuvm._reg.uvm_reg_model.uvm_reg_cvr_t, accessor: pyuvm._s05_base_classes.uvm_object = None) → None

abstractmethod build_coverage(models: pyuvm._reg.uvm_reg_model.uvm_reg_cvr_t) → pyuvm._reg.uvm_reg_model.uvm_reg_cvr_t

abstractmethod add_coverage(models: pyuvm._reg.uvm_reg_model.uvm_reg_cvr_t) → None

abstractmethod has_coverage(models: pyuvm._reg.uvm_reg_model.uvm_reg_cvr_t) → bool

abstractmethod set_coverage(is_on: pyuvm._reg.uvm_reg_model.uvm_reg_cvr_t) → pyuvm._reg.uvm_reg_model.uvm_reg_cvr_t

abstractmethod get_coverage(is_on: pyuvm._reg.uvm_reg_model.uvm_reg_cvr_t) → bool

abstractmethod sample(data: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, byte_en: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, is_read: bool, map: pyuvm._reg.uvm_reg_map.uvm_reg_map) → None

abstractmethod sample_values() → None

_sample(data: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, byte_en: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, is_read: bool, map: pyuvm._reg.uvm_reg_map.uvm_reg_map) → None

abstractmethod async pre_write(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

abstractmethod async post_write(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

abstractmethod async pre_read(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

abstractmethod async post_read(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

get_reg_size() → int

property n_bits: int

check_err_list() → None

_set_lock() → None

set_desired(value)

get_desired()

get_access_policy()

class pyuvm.uvm_reg_adapter(name: str = '')

get_item() → pyuvm._reg.uvm_reg_item.uvm_reg_item

set_item(item: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

reg2bus(rw: pyuvm._reg.uvm_reg_item.uvm_reg_bus_op) → pyuvm._s14_15_python_sequences.uvm_sequence_item

bus2reg(bus_item: pyuvm._s14_15_python_sequences.uvm_sequence_item, rw: pyuvm._reg.uvm_reg_item.uvm_reg_bus_op) → None

class pyuvm.uvm_reg_tlm_adapter(name: str = 'uvm_reg_tlm_adapter')

Bases: pyuvm._reg.uvm_reg_adapter.uvm_reg_adapter

abstractmethod reg2bus(rw: pyuvm._reg.uvm_reg_item.uvm_reg_bus_op) → pyuvm._s14_15_python_sequences.uvm_sequence_item

abstractmethod bus2reg(bus_item: pyuvm._s14_15_python_sequences.uvm_sequence_item, rw: pyuvm._reg.uvm_reg_item.uvm_reg_bus_op) → None

class pyuvm.uvm_reg_backdoor(name: str = '')

abstractmethod async do_pre_read(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

abstractmethod async do_post_read(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

abstractmethod async do_pre_write(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

abstractmethod async do_post_write(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

abstractmethod async write(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

abstractmethod async read(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

abstractmethod read_func(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

abstractmethod is_auto_updated(field: pyuvm._reg.uvm_reg_field.uvm_reg_field) → bool

abstractmethod async wait_for_change() → None

abstractmethod async pre_read(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

abstractmethod async post_read(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

abstractmethod async pre_write(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

abstractmethod async post_write(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

class pyuvm.uvm_reg_block(name: str = '', has_coverage: int = uvm_coverage_model_e.UVM_NO_COVERAGE)

_root_names: ClassVar[list[str]]: ‘list(…)’

_roots: ClassVar[list[pyuvm._reg.uvm_reg_block.uvm_reg_block]]: ‘list(…)’

_enable_reg_lookup_cache: ClassVar[bool]: False

_reg_block_registry: ClassVar[dict[str, pyuvm._reg.uvm_reg_block.uvm_reg_block]]: ‘dict(…)’

configure(parent: pyuvm._reg.uvm_reg_block.uvm_reg_block = None, hdl_path: str = '') → None

create_map(name: str, base_addr: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, n_bytes: int, endian: pyuvm._reg.uvm_reg_model.uvm_endianness_e, byte_addressing: bool = True) → pyuvm._reg.uvm_reg_map.uvm_reg_map

abstractmethod static check_data_width(width: int) → bool

set_default_map(map: pyuvm._reg.uvm_reg_map.uvm_reg_map) → None

get_default_map() → pyuvm._reg.uvm_reg_map.uvm_reg_map

set_parent(parent: pyuvm._reg.uvm_reg_block.uvm_reg_block) → None

_add_block(blk: pyuvm._reg.uvm_reg_block.uvm_reg_block) → None

_add_map(map: pyuvm._reg.uvm_reg_map.uvm_reg_map) → None

_add_register(reg: pyuvm._reg.uvm_reg.uvm_reg) → None

abstractmethod _add_virtual_register(vreg: pyuvm._reg.uvm_vreg.uvm_vreg) → None

lock_model() → None

abstractmethod unlock_model() → None

async wait_for_lock() → None

is_locked() → bool

get_full_name() → str

get_parent() → pyuvm._reg.uvm_reg_block.uvm_reg_block

abstractmethod static get_root_blocks() → list[pyuvm._reg.uvm_reg_block.uvm_reg_block]

abstractmethod static find_blocks(name: str, root: pyuvm._reg.uvm_reg_block.uvm_reg_block = None, accessor: pyuvm._s05_base_classes.uvm_object = None) → list[pyuvm._reg.uvm_reg_block.uvm_reg_block]

get_blocks(hier: pyuvm._reg.uvm_reg_model.uvm_hier_e = uvm_hier_e.UVM_HIER) → list[pyuvm._reg.uvm_reg_block.uvm_reg_block]

get_maps() → list[pyuvm._reg.uvm_reg_map.uvm_reg_map]

get_registers(hier: pyuvm._reg.uvm_reg_model.uvm_hier_e = uvm_hier_e.UVM_HIER) → list[pyuvm._reg.uvm_reg.uvm_reg]

get_fields(hier: pyuvm._reg.uvm_reg_model.uvm_hier_e = uvm_hier_e.UVM_HIER) → list[pyuvm._reg.uvm_reg_field.uvm_reg_field]

get_memories(hier: pyuvm._reg.uvm_reg_model.uvm_hier_e = uvm_hier_e.UVM_HIER) → list[pyuvm._reg.uvm_mem.uvm_mem]

get_virtual_registers(hier: pyuvm._reg.uvm_reg_model.uvm_hier_e = uvm_hier_e.UVM_HIER) → list[pyuvm._reg.uvm_vreg.uvm_vreg]

get_virtual_fields(hier: pyuvm._reg.uvm_reg_model.uvm_hier_e = uvm_hier_e.UVM_HIER) → list[pyuvm._reg.uvm_vreg_field.uvm_vreg_field]

get_block_by_name(name: str) → pyuvm._reg.uvm_reg_block.uvm_reg_block | None

static get_block_by_full_name(name: str) → pyuvm._reg.uvm_reg_block.uvm_reg_block | None

get_map_by_name(name: str) → pyuvm._reg.uvm_reg_map.uvm_reg_map

get_reg_by_name(name: str) → pyuvm._reg.uvm_reg.uvm_reg | None

get_field_by_name(name: str) → pyuvm._reg.uvm_reg_field.uvm_reg_field

get_mem_by_name(name: str) → pyuvm._reg.uvm_mem.uvm_mem | None

get_vreg_by_name(name: str) → pyuvm._reg.uvm_vreg.uvm_vreg | None

get_vfield_by_name(name: str) → pyuvm._reg.uvm_vreg_field.uvm_vreg_field

abstractmethod build_coverage(models: pyuvm._reg.uvm_reg_model.uvm_reg_cvr_t) → pyuvm._reg.uvm_reg_model.uvm_reg_cvr_t

abstractmethod add_coverage(models: pyuvm._reg.uvm_reg_model.uvm_reg_cvr_t) → None

abstractmethod has_coverage(models: pyuvm._reg.uvm_reg_model.uvm_reg_cvr_t) → bool

abstractmethod set_coverage(is_on: pyuvm._reg.uvm_reg_model.uvm_reg_cvr_t) → pyuvm._reg.uvm_reg_model.uvm_reg_cvr_t

abstractmethod get_coverage(is_on: pyuvm._reg.uvm_reg_model.uvm_reg_cvr_t = uvm_coverage_model_e.UVM_CVR_ALL) → bool

abstractmethod sample(offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, is_read: bool, map: pyuvm._reg.uvm_reg_map.uvm_reg_map) → None

abstractmethod sample_values() → None

abstractmethod _sample(addr: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, is_read: bool, map: pyuvm._reg.uvm_reg_map.uvm_reg_map) → None

get_default_door() → pyuvm._reg.uvm_reg_model.uvm_door_e

set_default_door(door: pyuvm._reg.uvm_reg_model.uvm_door_e) → None

get_default_path() → pyuvm._reg.uvm_reg_model.uvm_path_e

reset(kind: str = 'HARD') → None

abstractmethod needs_update() → bool

abstractmethod async update(path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_DEFAULT_DOOR, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, prior: int = -1, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → pyuvm._reg.uvm_reg_model.uvm_status_e

abstractmethod async mirror(check: pyuvm._reg.uvm_reg_model.uvm_check_e = uvm_check_e.UVM_NO_CHECK, path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_DEFAULT_DOOR, parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, prior: int = -1, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → pyuvm._reg.uvm_reg_model.uvm_status_e

abstractmethod async write_reg_by_name(name: str, data: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_DEFAULT_DOOR, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, prior: int = -1, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → pyuvm._reg.uvm_reg_model.uvm_status_e

abstractmethod async read_reg_by_name(name: str, path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_DEFAULT_DOOR, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, prior: int = -1, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → tuple[pyuvm._reg.uvm_reg_model.uvm_status_e, pyuvm._reg.uvm_reg_model.uvm_reg_data_t]

abstractmethod async write_mem_by_name(name: str, offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, data: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_DEFAULT_DOOR, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, prior: int = -1, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → pyuvm._reg.uvm_reg_model.uvm_status_e

abstractmethod async read_mem_by_name(name: str, offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_DEFAULT_DOOR, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, prior: int = -1, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → tuple[pyuvm._reg.uvm_reg_model.uvm_status_e, pyuvm._reg.uvm_reg_model.uvm_reg_data_t]

abstractmethod async readmemh() → None

abstractmethod async writememh() → None

abstractmethod get_backdoor(inherited: bool = True) → pyuvm._reg.uvm_reg_backdoor.uvm_reg_backdoor

abstractmethod set_backdoor(bkdr: pyuvm._reg.uvm_reg_backdoor.uvm_reg_backdoor, fname: str = '', lineno: int = 0) → None

abstractmethod clear_hdl_path(kind: str = 'RTL') → None

add_hdl_path(path: str, kind: str = 'RTL') → None

abstractmethod has_hdl_path(kind: str = '') → bool

abstractmethod get_hdl_path(paths: list[str], kind: str = '') → None

abstractmethod get_full_hdl_path(paths: list[str], kind: str = '', separator: str = '.') → None

abstractmethod set_default_hdl_path(kind: str) → None

abstractmethod get_default_hdl_path() → str

abstractmethod set_hdl_path_root(path: str, kind: str = 'RTL') → None

abstractmethod is_hdl_path_root(kind: str = '') → bool

_init_address_maps() → None

set_lock(v: bool = None) → None

abstractmethod _unregister(m: pyuvm._reg.uvm_reg_map.uvm_reg_map) → None

add_block(blk: pyuvm._reg.uvm_reg_block.uvm_reg_block) → None

class pyuvm.uvm_reg_cbs(name: str = 'uvm_reg_cbs'): Bases: pyuvm._s10_synchronization_classes.uvm_callback

class pyuvm.uvm_reg_cb(name: str = 'uvm_callbacks'): Bases: pyuvm._s10_synchronization_classes.uvm_callbacks

class pyuvm.uvm_reg_cb_iter(obj: type[pyuvm._s05_base_classes.uvm_object] | pyuvm._s05_base_classes.uvm_object)

Bases: pyuvm._s10_synchronization_classes.uvm_callback_iter

Initialization

class pyuvm.uvm_reg_bd_cb(name: str = 'uvm_callbacks'): Bases: pyuvm._s10_synchronization_classes.uvm_callbacks

class pyuvm.uvm_reg_bd_cb_iter(obj: type[pyuvm._s05_base_classes.uvm_object] | pyuvm._s05_base_classes.uvm_object)

Bases: pyuvm._s10_synchronization_classes.uvm_callback_iter

Initialization

class pyuvm.uvm_mem_cb(name: str = 'uvm_callbacks'): Bases: pyuvm._s10_synchronization_classes.uvm_callbacks

class pyuvm.uvm_mem_cb_iter(obj: type[pyuvm._s05_base_classes.uvm_object] | pyuvm._s05_base_classes.uvm_object)

Bases: pyuvm._s10_synchronization_classes.uvm_callback_iter

Initialization

class pyuvm.uvm_reg_field_cb(name: str = 'uvm_callbacks'): Bases: pyuvm._s10_synchronization_classes.uvm_callbacks

class pyuvm.uvm_reg_field_cb_iter(obj: type[pyuvm._s05_base_classes.uvm_object] | pyuvm._s05_base_classes.uvm_object)

Bases: pyuvm._s10_synchronization_classes.uvm_callback_iter

Initialization

class pyuvm.uvm_reg_read_only_cbs(name: str = 'uvm_reg_read_only_cbs'): Bases: pyuvm._reg.uvm_reg_cbs.uvm_reg_cbs

class pyuvm.uvm_reg_write_only_cbs(name: str = 'uvm_reg_write_only_cbs'): Bases: pyuvm._reg.uvm_reg_cbs.uvm_reg_cbs

class pyuvm.uvm_reg_field(name: str = 'uvm_reg_field')

_max_size: ClassVar[int]: 0

_policy_names: ClassVar[set[str]]: None

_reg_field_registry: ClassVar[dict[str, pyuvm._reg.uvm_reg_field.uvm_reg_field]]: ‘dict(…)’

configure(parent: pyuvm._reg.uvm_reg.uvm_reg, size: int, lsb_pos: int, access: str, volatile: bool, reset: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, has_reset: bool = None, is_rand: bool = None, individually_accessible: bool = None, **kwargs) → None

get_full_name() → str

get_parent() → pyuvm._reg.uvm_reg.uvm_reg

get_register() → pyuvm._reg.uvm_reg.uvm_reg

get_lsb_pos() → int

get_n_bits() → int

static get_max_size() → int

set_access(mode: str) → str

set_rand_mode(rand_mode: bool) → None

static define_access(name: str) → bool

get_access(map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None) → str | None

is_known_access(map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None) → bool

set_volatility(volatile: bool) → None

is_volatile() → bool

static get_field_by_full_name(name: str) → pyuvm._reg.uvm_reg_field.uvm_reg_field

set_field(value: int) → None

set(value: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, fname: str = '', lineno: int = 0) → None

get(fname: str = '', lineno: int = 0) → pyuvm._reg.uvm_reg_model.uvm_reg_data_t

get_mirrored_value(fname: str = '', lineno: int = 0) → pyuvm._reg.uvm_reg_model.uvm_reg_data_t

reset(kind: str = 'HARD') → None

get_reset(kind: str = 'HARD') → pyuvm._reg.uvm_reg_model.uvm_reg_data_t

has_reset(kind: str = 'HARD', delete: bool = False) → bool

set_reset(value: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, kind: str = 'HARD') → None

needs_update() → bool

abstractmethod async write(value: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_DEFAULT_DOOR, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, prior: int = -1, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → pyuvm._reg.uvm_reg_model.uvm_status_e

abstractmethod async read(path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_DEFAULT_DOOR, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, prior: int = -1, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → tuple[pyuvm._reg.uvm_reg_model.uvm_status_e, pyuvm._reg.uvm_reg_model.uvm_reg_data_t]

abstractmethod async poke(value: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, kind: str = '', parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → pyuvm._reg.uvm_reg_model.uvm_status_e

abstractmethod async peek(kind: str = '', parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → tuple[pyuvm._reg.uvm_reg_model.uvm_status_e, pyuvm._reg.uvm_reg_model.uvm_reg_data_t]

abstractmethod async mirror(check: pyuvm._reg.uvm_reg_model.uvm_check_e = uvm_check_e.UVM_NO_CHECK, path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_DEFAULT_DOOR, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, prior: int = -1, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → pyuvm._reg.uvm_reg_model.uvm_status_e

set_compare(check: pyuvm._reg.uvm_reg_model.uvm_check_e) → None

get_compare() → pyuvm._reg.uvm_reg_model.uvm_check_e

abstractmethod is_indv_accessible(path: pyuvm._reg.uvm_reg_model.uvm_door_e, local_map: pyuvm._reg.uvm_reg_map.uvm_reg_map) → bool

predict(value: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, be: pyuvm._reg.uvm_reg_model.uvm_reg_byte_en_t = -1, kind: pyuvm._reg.uvm_reg_model.uvm_predict_e = uvm_predict_e.UVM_PREDICT_DIRECT, path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_FRONTDOOR, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, fname: str = '', lineno: int = 0) → bool

_predict(cur_val: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, wr_val: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, map: pyuvm._reg.uvm_reg_map.uvm_reg_map) → pyuvm._reg.uvm_reg_model.uvm_reg_data_t

abstractmethod _update() → pyuvm._reg.uvm_reg_model.uvm_reg_data_t

abstractmethod _check_access(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item, map_info: pyuvm._reg.uvm_reg_map.uvm_reg_map_info) → bool

abstractmethod async do_write(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

abstractmethod async do_read(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

do_predict(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item, kind: pyuvm._reg.uvm_reg_model.uvm_predict_e = uvm_predict_e.UVM_PREDICT_DIRECT, be: pyuvm._reg.uvm_reg_model.uvm_reg_byte_en_t = -1) → None

abstractmethod pre_randomize() → None

abstractmethod post_randomize() → None

abstractmethod async pre_write(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

abstractmethod async post_write(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

abstractmethod async pre_read(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

abstractmethod async post_read(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

field_lock() → None

get_value() → pyuvm._reg.uvm_reg_model.uvm_reg_data_t

set_response(f_response)

get_response()

set_throw_error_on_read(teor=False)

set_throw_error_on_write(teow=False)

set_debug(error_on_read=None, error_on_write=None)

class pyuvm.uvm_reg_fifo(name: str = 'uvm_reg_fifo', size: int = 0, n_bits: int = 0, has_coverage: int = 0)

Bases: pyuvm._reg.uvm_reg.uvm_reg

abstractmethod build() → None

abstractmethod set_compare(check: pyuvm._reg.uvm_reg_model.uvm_check_e = uvm_check_e.UVM_CHECK) → None

abstractmethod size() → int

abstractmethod capacity() → int

abstractmethod set(value: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, fname: str = '', lineno: int = 0) → None

abstractmethod async update(path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_DEFAULT_DOOR, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, prior: int = -1, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → pyuvm._reg.uvm_reg_model.uvm_status_e

abstractmethod get(fname: str = '', lineno: int = 0) → pyuvm._reg.uvm_reg_model.uvm_reg_data_t

abstractmethod do_predict(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item, kind: pyuvm._reg.uvm_reg_model.uvm_predict_e = uvm_predict_e.UVM_PREDICT_DIRECT, be: pyuvm._reg.uvm_reg_model.uvm_reg_byte_en_t = -1) → bool

abstractmethod async pre_write(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

abstractmethod async pre_read(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

abstractmethod post_randomize() → None

class pyuvm.uvm_reg_file(name: str = '')

abstractmethod configure(blk_parent: pyuvm._reg.uvm_reg_block.uvm_reg_block, regfile_parent: pyuvm._reg.uvm_reg_file.uvm_reg_file, hdl_path: str = '') → None

abstractmethod get_full_name() → str

abstractmethod get_parent() → pyuvm._reg.uvm_reg_block.uvm_reg_block

abstractmethod get_block() → pyuvm._reg.uvm_reg_block.uvm_reg_block

abstractmethod get_regfile() → pyuvm._reg.uvm_reg_file.uvm_reg_file

abstractmethod clear_hdl_path(kind: str = 'RTL') → None

abstractmethod add_hdl_path(path: str, kind: str = 'RTL') → None

abstractmethod has_hdl_path(kind: str = '') → bool

abstractmethod get_hdl_path(paths: list[str], kind: str = '') → None

abstractmethod get_full_hdl_path(paths: list[str], kind: str = '', separator: str = '.') → None

abstractmethod set_default_hdl_path(kind: str) → None

abstractmethod get_default_hdl_path() → str

class pyuvm.uvm_reg_indirect_data(name: str = 'uvm_reg_indirect', n_bits: int = 0, has_coverage: int = 0): Bases: pyuvm._reg.uvm_reg.uvm_reg

class pyuvm.uvm_reg_indirect_ftdr_seq(addr_reg: pyuvm._reg.uvm_reg.uvm_reg, idx: int, data_reg: pyuvm._reg.uvm_reg.uvm_reg): Bases: pyuvm._reg.uvm_reg_sequence.uvm_reg_frontdoor

class pyuvm.uvm_reg_item(name: str = '')

Bases: pyuvm._s14_15_python_sequences.uvm_sequence_item

set_element_kind(element_kind: pyuvm._reg.uvm_reg_model.uvm_elem_kind_e) → None

get_element_kind() → pyuvm._reg.uvm_reg_model.uvm_elem_kind_e

set_element(element: pyuvm._s05_base_classes.uvm_object) → None

get_element() → pyuvm._s05_base_classes.uvm_object

set_kind(kind: pyuvm._reg.uvm_reg_model.uvm_access_e) → None

get_kind() → pyuvm._reg.uvm_reg_model.uvm_access_e

set_value(value: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, idx: int = 0) → None

get_value(idx: int = 0) → pyuvm._reg.uvm_reg_model.uvm_reg_data_t

set_value_size(sz: int) → None

get_value_size() → int

set_value_array(value: list[pyuvm._reg.uvm_reg_model.uvm_reg_data_t]) → None

get_value_array() → list[pyuvm._reg.uvm_reg_model.uvm_reg_data_t]

set_offset(offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t) → None

get_offset() → pyuvm._reg.uvm_reg_model.uvm_reg_addr_t

set_status(status: pyuvm._reg.uvm_reg_model.uvm_status_e) → None

get_status() → pyuvm._reg.uvm_reg_model.uvm_status_e

set_local_map(map: pyuvm._reg.uvm_reg_map.uvm_reg_map) → None

get_local_map() → pyuvm._reg.uvm_reg_map.uvm_reg_map

set_map(map: pyuvm._reg.uvm_reg_map.uvm_reg_map) → None

get_map() → pyuvm._reg.uvm_reg_map.uvm_reg_map

set_door(door: pyuvm._reg.uvm_reg_model.uvm_door_e) → None

get_door() → pyuvm._reg.uvm_reg_model.uvm_door_e

set_parent_sequence(parent: pyuvm._s14_15_python_sequences.uvm_sequence_base) → None

get_parent_sequence() → pyuvm._s14_15_python_sequences.uvm_sequence_base

set_priority(value: int) → None

get_priority() → int

set_extension(value: pyuvm._s05_base_classes.uvm_object) → None

get_extension() → pyuvm._s05_base_classes.uvm_object

set_bd_kind(bd_kind: str) → None

get_bd_kind() → str

set_fname(fname: str) → None

get_fname() → str

set_line(line: int) → None

get_line() → int

class pyuvm.uvm_reg_bus_op

kind: pyuvm._reg.uvm_reg_model.uvm_access_e: None

addr: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t: 0

data: pyuvm._reg.uvm_reg_model.uvm_reg_data_t: 0

n_bits: int: 0

byte_en: pyuvm._reg.uvm_reg_model.uvm_reg_byte_en_t: 0

status: pyuvm._reg.uvm_reg_model.uvm_status_e: None

class pyuvm.uvm_reg_map_info: Initialization

class pyuvm.uvm_reg_transaction_order_policy(name: str = 'policy')

abstractmethod order(q: list[pyuvm._reg.uvm_reg_item.uvm_reg_bus_op]) → None

class pyuvm.uvm_reg_seq_base(name: str = 'uvm_reg_seq_base'): Bases: pyuvm._s14_15_python_sequences.uvm_sequence_base

class pyuvm.uvm_reg_map(name: str = 'uvm_reg_map')

_backdoor: ClassVar[pyuvm._reg.uvm_reg_backdoor.uvm_reg_backdoor | None]: None

_init_address_map() → None

static backdoor() → pyuvm._reg.uvm_reg_backdoor.uvm_reg_backdoor

configure(parent: pyuvm._reg.uvm_reg_block.uvm_reg_block, base_addr: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, n_bytes: int = None, endian: pyuvm._reg.uvm_reg_model.uvm_endianness_e = None, byte_addressing: bool = True) → None

add_reg(rg: pyuvm._reg.uvm_reg.uvm_reg, offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, rights: str = 'RW', unmapped: bool = False, frontdoor: pyuvm._reg.uvm_reg_sequence.uvm_reg_frontdoor = None) → None

abstractmethod add_mem(mem: pyuvm._reg.uvm_mem.uvm_mem, offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, rights: str = 'RW', unmapped: bool = False, frontdoor: pyuvm._reg.uvm_reg_sequence.uvm_reg_frontdoor = None)

add_submap(child_map: pyuvm._reg.uvm_reg_map.uvm_reg_map, offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t) → None

set_sequencer(sequencer: pyuvm.uvm_sequencer, adapter: pyuvm._reg.uvm_reg_adapter.uvm_reg_adapter = None) → None

set_submap_offset(submap: pyuvm._reg.uvm_reg_map.uvm_reg_map, offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t) → None

get_submap_offset(submap: pyuvm._reg.uvm_reg_map.uvm_reg_map) → pyuvm._reg.uvm_reg_model.uvm_reg_addr_t

abstractmethod set_base_addr(offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t) → None

reset(kind: str = 'SOFT') → None

_add_parent_map(parent_map: pyuvm._reg.uvm_reg_map.uvm_reg_map, offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t) → None

abstractmethod _verify_map_config() → None

_set_reg_offset(reg: pyuvm._reg.uvm_reg.uvm_reg, offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, unmapped: bool) → None

abstractmethod _set_mem_offset(mem: pyuvm._reg.uvm_mem.uvm_mem, offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, unmapped: bool) → None

get_full_name() → str

get_root_map() → pyuvm._reg.uvm_reg_map.uvm_reg_map

get_parent() → pyuvm._reg.uvm_reg_block.uvm_reg_block

get_parent_map() → pyuvm._reg.uvm_reg_map.uvm_reg_map

get_base_addr(hier: pyuvm._reg.uvm_reg_model.uvm_hier_e = uvm_hier_e.UVM_HIER) → pyuvm._reg.uvm_reg_model.uvm_reg_addr_t

get_n_bytes(hier: pyuvm._reg.uvm_reg_model.uvm_hier_e = uvm_hier_e.UVM_HIER) → int

get_addr_unit_bytes() → int

get_endian(hier: pyuvm._reg.uvm_reg_model.uvm_hier_e = uvm_hier_e.UVM_HIER) → pyuvm._reg.uvm_reg_model.uvm_endianness_e

get_sequencer(hier: pyuvm._reg.uvm_reg_model.uvm_hier_e = uvm_hier_e.UVM_HIER) → pyuvm.uvm_sequencer_base

get_adapter(hier: pyuvm._reg.uvm_reg_model.uvm_hier_e = uvm_hier_e.UVM_HIER) → pyuvm._reg.uvm_reg_adapter.uvm_reg_adapter

get_submaps(hier: pyuvm._reg.uvm_reg_model.uvm_hier_e = uvm_hier_e.UVM_HIER) → list[pyuvm._reg.uvm_reg_map.uvm_reg_map]

get_registers(hier: pyuvm._reg.uvm_reg_model.uvm_hier_e = uvm_hier_e.UVM_HIER) → list[pyuvm._reg.uvm_reg.uvm_reg]

get_fields(hier: pyuvm._reg.uvm_reg_model.uvm_hier_e = uvm_hier_e.UVM_HIER) → list[pyuvm._reg.uvm_reg_field.uvm_reg_field]

get_memories(hier: pyuvm._reg.uvm_reg_model.uvm_hier_e = uvm_hier_e.UVM_HIER) → list[pyuvm._reg.uvm_mem.uvm_mem]

get_virtual_registers(hier: pyuvm._reg.uvm_reg_model.uvm_hier_e = uvm_hier_e.UVM_HIER) → list[pyuvm._reg.uvm_vreg.uvm_vreg]

get_virtual_fields(hier: pyuvm._reg.uvm_reg_model.uvm_hier_e = uvm_hier_e.UVM_HIER) → list[pyuvm._reg.uvm_vreg_field.uvm_vreg_field]

get_reg_map_info(rg: pyuvm._reg.uvm_reg.uvm_reg, error: bool = True) → pyuvm._reg.uvm_reg_map.uvm_reg_map_info | None

abstractmethod get_mem_map_info(mem: pyuvm._reg.uvm_mem.uvm_mem, error: bool) → pyuvm._reg.uvm_reg_map.uvm_reg_map_info

abstractmethod get_size() → int

get_physical_addresses(base_addr: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, mem_offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, n_bytes: int) → tuple[int, list[pyuvm._reg.uvm_reg_model.uvm_reg_addr_t]]

get_reg_by_offset(offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, read: bool = True) → pyuvm._reg.uvm_reg.uvm_reg | None

abstractmethod get_mem_by_offset(offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t) → pyuvm._reg.uvm_mem.uvm_mem

set_auto_predict(on: bool = True) → None

get_auto_predict() → bool

set_check_on_read(on: bool = True) → None

get_check_on_read() → bool

async do_bus_write(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item, sequencer: pyuvm.uvm_sequencer_base, adapter: pyuvm._reg.uvm_reg_adapter.uvm_reg_adapter) → None

async do_bus_read(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item, sequencer: pyuvm.uvm_sequencer_base, adapter: pyuvm._reg.uvm_reg_adapter.uvm_reg_adapter) → None

async do_write(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

async do_read(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

_get_bus_info(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → tuple[pyuvm._reg.uvm_reg_map.uvm_reg_map_info, int, int, int]

set_transaction_order_policy(pol: pyuvm._reg.uvm_reg_map.uvm_reg_transaction_order_policy) → None

get_transaction_order_policy() → pyuvm._reg.uvm_reg_map.uvm_reg_transaction_order_policy

_get_physical_addresses_to_map(base_addr: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, mem_offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, n_bytes: int, parent_map: pyuvm._reg.uvm_reg_map.uvm_reg_map, mem: pyuvm._reg.uvm_mem.uvm_mem = None) → tuple[int, list[pyuvm._reg.uvm_reg_model.uvm_reg_addr_t], int]

abstractmethod async perform_accesses(accesses: list[pyuvm._reg.uvm_reg_item.uvm_reg_bus_op], rw: pyuvm._reg.uvm_reg_item.uvm_reg_item, adapter: pyuvm._reg.uvm_reg_adapter.uvm_reg_adapter, sequencer: pyuvm.uvm_sequencer_base) → None

abstractmethod unregister() → None

abstractmethod clone_and_update(rights: str) → pyuvm._reg.uvm_reg_map.uvm_reg_map

get_offset() → pyuvm._reg.uvm_reg_model.uvm_reg_addr_t

set_adapter(adapter) → None

class pyuvm.uvm_reg_data_t: Bases: int

class pyuvm.uvm_reg_data_logic_t: Bases: int

class pyuvm.uvm_reg_addr_t: Bases: int

class pyuvm.uvm_reg_addr_logic_t: Bases: int

class pyuvm.uvm_reg_byte_en_t: Bases: int

class pyuvm.uvm_reg_cvr_t: Bases: int

class pyuvm.uvm_hdl_path_slice(name='')

path: str: None

offset: int: None

size: int: None

class pyuvm.uvm_status_e(*args, **kwds)

Bases: enum.Enum

UVM_IS_OK: 0

UVM_NOT_OK: 1

UVM_HAS_X: 2

class pyuvm.uvm_door_e(*args, **kwds)

Bases: enum.Enum

UVM_FRONTDOOR: 0

UVM_BACKDOOR: 1

UVM_PREDICT: 2

UVM_DEFAULT_DOOR: 3

class pyuvm.uvm_path_e(*args, **kwds): Bases: enum.Enum

class pyuvm.uvm_check_e(*args, **kwds)

Bases: enum.Enum

UVM_NO_CHECK: 0

UVM_CHECK: 1

class pyuvm.uvm_endianness_e(*args, **kwds)

Bases: enum.Enum

UVM_NO_ENDIAN: 0

UVM_LITTLE_ENDIAN: 1

UVM_BIG_ENDIAN: 2

UVM_LITTLE_FIFO: 3

UVM_BIG_FIFO: 4

class pyuvm.uvm_elem_kind_e(*args, **kwds)

Bases: enum.Enum

UVM_REG: 0

UVM_FIELD: 1

UVM_MEM: 2

class pyuvm.uvm_access_e(*args, **kwds)

Bases: enum.Enum

UVM_READ: 0

UVM_WRITE: 1

UVM_BURST_READ: 2

UVM_BURST_WRITE: 3

class pyuvm.uvm_hier_e(*args, **kwds)

Bases: enum.Enum

UVM_NO_HIER: 0

UVM_HIER: 1

class pyuvm.uvm_predict_e(*args, **kwds)

Bases: enum.Enum

UVM_PREDICT_DIRECT: 0

UVM_PREDICT_READ: 1

UVM_PREDICT_WRITE: 2

class pyuvm.uvm_coverage_model_e(*args, **kwds)

Bases: enum.Enum

UVM_NO_COVERAGE: 0

UVM_CVR_REG_BITS: 1

UVM_CVR_ADDR_MAP: 2

UVM_CVR_FIELD_VALS: 4

UVM_CVR_ALL: None

class pyuvm.uvm_reg_mem_test_e

Bases: enum.IntEnum

UVM_DO_REG_HW_RESET: 1

UVM_DO_REG_BIT_BASH: 2

UVM_DO_REG_ACCESS: 4

UVM_DO_MEM_ACCESS: 8

UVM_DO_SHARED_ACCESS: 16

UVM_DO_MEM_WALK: 32

UVM_DO_ALL_REG_MEM_TESTS: 18446744073709551615

class pyuvm.uvm_hdl_path_concat(name: str = ''): Bases: pyuvm._s05_base_classes.uvm_object

class pyuvm.uvm_reg_frontdoor: Initialization

class pyuvm.uvm_reg_map_addr_range: Initialization

class pyuvm.uvm_object_string_pool(name: str = ''): Bases: pyuvm._s05_base_classes.uvm_object

class pyuvm.uvm_reg_predictor(name: str, parent: pyuvm._s13_uvm_component.uvm_component)

abstractmethod pre_predict(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

check_phase(phase: pyuvm.uvm_phase)

flush() → None

class pyuvm.uvm_reg_sequence(name: str = 'uvm_reg_sequence_inst')

Bases: pyuvm._s14_15_python_sequences.uvm_sequence

abstractmethod async body()

abstractmethod async do_reg_item(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

abstractmethod async write_reg(rg: pyuvm._reg.uvm_reg.uvm_reg, value: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_DEFAULT_DOOR, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, prior: int = -1, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → pyuvm._reg.uvm_reg_model.uvm_status_e

abstractmethod async read_reg(rg: pyuvm._reg.uvm_reg.uvm_reg, path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_DEFAULT_DOOR, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, prior: int = -1, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → tuple[pyuvm._reg.uvm_reg_model.uvm_status_e, pyuvm._reg.uvm_reg_model.uvm_reg_data_t]

abstractmethod async poke_reg(rg: pyuvm._reg.uvm_reg.uvm_reg, value: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, kind: str = '', extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → pyuvm._reg.uvm_reg_model.uvm_status_e

abstractmethod async peek_reg(rg: pyuvm._reg.uvm_reg.uvm_reg, kind: str = '', extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → tuple[pyuvm._reg.uvm_reg_model.uvm_status_e, pyuvm._reg.uvm_reg_model.uvm_reg_data_t]

abstractmethod async update_reg(rg: pyuvm._reg.uvm_reg.uvm_reg, path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_DEFAULT_DOOR, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, prior: int = -1, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → pyuvm._reg.uvm_reg_model.uvm_status_e

abstractmethod async mirror_reg(rg: pyuvm._reg.uvm_reg.uvm_reg, check: pyuvm._reg.uvm_reg_model.uvm_check_e = uvm_check_e.UVM_NO_CHECK, path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_DEFAULT_DOOR, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, prior: int = -1, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → pyuvm._reg.uvm_reg_model.uvm_status_e

abstractmethod async write_mem(mem: pyuvm._reg.uvm_mem, offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, value: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_DEFAULT_DOOR, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, prior: int = -1, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → pyuvm._reg.uvm_reg_model.uvm_status_e

abstractmethod async read_mem(mem: pyuvm._reg.uvm_mem, offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_DEFAULT_DOOR, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, prior: int = -1, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → tuple[pyuvm._reg.uvm_reg_model.uvm_status_e, pyuvm._reg.uvm_reg_model.uvm_reg_data_t]

abstractmethod async poke_mem(mem: pyuvm._reg.uvm_mem, offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, value: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, kind: str = '', extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → pyuvm._reg.uvm_reg_model.uvm_status_e

abstractmethod async peek_mem(mem: pyuvm._reg.uvm_mem, offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, kind: str = '', extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → tuple[pyuvm._reg.uvm_reg_model.uvm_status_e, pyuvm._reg.uvm_reg_model.uvm_reg_data_t]

class pyuvm.uvm_vreg(name: str, n_bits: int)

abstractmethod configure(parent: pyuvm._reg.uvm_reg_block.uvm_reg_block, mem: pyuvm._reg.uvm_mem.uvm_mem = None, size: int = 0, offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t = 0, incr: int = 0) → None

abstractmethod implement(mem: pyuvm._reg.uvm_mem.uvm_mem = None, offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t = 0, incr: int = 0) → None

abstractmethod allocate(n: int, mam: pyuvm._reg.uvm_mem_mam.uvm_mem_mam, alloc: pyuvm._reg.uvm_mem_mam.uvm_mem_mam_policy = None) → None

abstractmethod get_region() → pyuvm._reg.uvm_mem_mam.uvm_mem_region

abstractmethod release_region() → None

abstractmethod get_full_name() → str

abstractmethod get_parent() → pyuvm._reg.uvm_reg_block.uvm_reg_block

abstractmethod get_block() → pyuvm._reg.uvm_reg_block.uvm_reg_block

abstractmethod get_memory() → pyuvm._reg.uvm_mem.uvm_mem

abstractmethod get_n_maps() → int

abstractmethod is_in_map(map: pyuvm._reg.uvm_reg_map.uvm_reg_map) → bool

abstractmethod get_maps(maps: list[pyuvm._reg.uvm_reg_map.uvm_reg_map]) → None

abstractmethod get_rights(map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None) → str

abstractmethod get_access(map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None) → str

abstractmethod get_size() → int

abstractmethod get_n_bytes() → int

abstractmethod get_incr() → int

abstractmethod get_n_memlocs() → int

abstractmethod get_fields(fields: list[pyuvm._reg.uvm_vreg_field.uvm_vreg_field]) → None

abstractmethod get_field_by_name(name: str) → pyuvm._reg.uvm_vreg_field.uvm_vreg_field

abstractmethod get_offset_in_memory(idx: int) → pyuvm._reg.uvm_reg_model.uvm_reg_addr_t

abstractmethod get_address(idx: int, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None) → pyuvm._reg.uvm_reg_model.uvm_reg_addr_t

abstractmethod async write(idx: int, value: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_DEFAULT_DOOR, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → pyuvm._reg.uvm_reg_model.uvm_status_e

abstractmethod async read(idx: int, path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_DEFAULT_DOOR, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → tuple[pyuvm._reg.uvm_reg_model.uvm_status_e, pyuvm._reg.uvm_reg_model.uvm_reg_data_t]

abstractmethod async poke(idx: int, value: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → pyuvm._reg.uvm_reg_model.uvm_status_e

abstractmethod async peek(idx: int, parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → tuple[pyuvm._reg.uvm_reg_model.uvm_status_e, pyuvm._reg.uvm_reg_model.uvm_reg_data_t]

abstractmethod async pre_write(idx: int, wdata: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, path: pyuvm._reg.uvm_reg_model.uvm_door_e, map: pyuvm._reg.uvm_reg_map.uvm_reg_map) → None

abstractmethod async post_write(idx: int, wdat: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, path: pyuvm._reg.uvm_reg_model.uvm_door_e, map: pyuvm._reg.uvm_reg_map.uvm_reg_map, status: pyuvm._reg.uvm_reg_model.uvm_status_e) → None

abstractmethod async pre_read(idx: int, path: pyuvm._reg.uvm_reg_model.uvm_door_e, map: pyuvm._reg.uvm_reg_map.uvm_reg_map) → None

abstractmethod async post_read(idx: int, rdat: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, path: pyuvm._reg.uvm_reg_model.uvm_door_e, map: pyuvm._reg.uvm_reg_map.uvm_reg_map, status: pyuvm._reg.uvm_reg_model.uvm_status_e) → None

class pyuvm.uvm_vreg_cbs(name: str = 'uvm_vreg_cbs')

Bases: pyuvm._s10_synchronization_classes.uvm_callback

abstractmethod async pre_write(rg: pyuvm._reg.uvm_vreg.uvm_vreg, idx: int, wdat: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, path: pyuvm._reg.uvm_reg_model.uvm_door_e, map: pyuvm._reg.uvm_reg_map.uvm_reg_map) → None

abstractmethod async post_write(rg: pyuvm._reg.uvm_vreg.uvm_vreg, idx: int, wdat: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, path: pyuvm._reg.uvm_reg_model.uvm_door_e, map: pyuvm._reg.uvm_reg_map.uvm_reg_map, status: pyuvm._reg.uvm_reg_model.uvm_status_e) → None

abstractmethod async pre_read(rg: pyuvm._reg.uvm_vreg.uvm_vreg, idx: int, path: pyuvm._reg.uvm_reg_model.uvm_door_e, map: pyuvm._reg.uvm_reg_map.uvm_reg_map) → None

abstractmethod async post_read(rg: pyuvm._reg.uvm_vreg.uvm_vreg, idx: int, rdat: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, path: pyuvm._reg.uvm_reg_model.uvm_door_e, map: pyuvm._reg.uvm_reg_map.uvm_reg_map, status: pyuvm._reg.uvm_reg_model.uvm_status_e) → None

class pyuvm.uvm_vreg_cb(name: str = 'uvm_callbacks'): Bases: pyuvm._s10_synchronization_classes.uvm_callbacks

class pyuvm.uvm_vreg_cb_iter(obj: type[pyuvm._s05_base_classes.uvm_object] | pyuvm._s05_base_classes.uvm_object)

Bases: pyuvm._s10_synchronization_classes.uvm_callback_iter

Initialization

class pyuvm.uvm_vreg_field(name: str = 'uvm_vreg_field')

abstractmethod configure(parent: pyuvm._reg.uvm_vreg.uvm_vreg, size: int, lsb_pos: int) → None

abstractmethod get_full_name() → str

abstractmethod get_parent() → pyuvm._reg.uvm_vreg.uvm_vreg

abstractmethod get_register() → pyuvm._reg.uvm_vreg.uvm_vreg

abstractmethod get_lsb_pos_in_register() → int

abstractmethod get_n_bits() → int

abstractmethod get_access(map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None) → str

abstractmethod async write(idx: int, value: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_DEFAULT_DOOR, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → pyuvm._reg.uvm_reg_model.uvm_status_e

abstractmethod async read(idx: int, path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_DEFAULT_DOOR, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → tuple[pyuvm._reg.uvm_reg_model.uvm_status_e, pyuvm._reg.uvm_reg_model.uvm_reg_data_t]

abstractmethod async poke(idx: int, value: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → pyuvm._reg.uvm_reg_model.uvm_status_e

abstractmethod async peek(idx: int, parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → tuple[pyuvm._reg.uvm_reg_model.uvm_status_e, pyuvm._reg.uvm_reg_model.uvm_reg_data_t]

abstractmethod async pre_write(idx: int, wdat: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, path: pyuvm._reg.uvm_reg_model.uvm_door_e, map: pyuvm._reg.uvm_reg_map.uvm_reg_map) → None

abstractmethod async post_write(idx: int, wdat: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, path: pyuvm._reg.uvm_reg_model.uvm_door_e, map: pyuvm._reg.uvm_reg_map.uvm_reg_map, status: pyuvm._reg.uvm_reg_model.uvm_status_e) → None

abstractmethod async pre_read(idx: int, path: pyuvm._reg.uvm_reg_model.uvm_door_e, map: pyuvm._reg.uvm_reg_map.uvm_reg_map) → None

abstractmethod async post_read(idx: int, rdat: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, path: pyuvm._reg.uvm_reg_model.uvm_door_e, map: pyuvm._reg.uvm_reg_map.uvm_reg_map, status: pyuvm._reg.uvm_reg_model.uvm_status_e) → None

class pyuvm.uvm_vreg_field_cbs(name: str = 'uvm_vreg_field_cbs')

Bases: pyuvm._s10_synchronization_classes.uvm_callback

abstractmethod async pre_write(field: pyuvm._reg.uvm_vreg_field.uvm_vreg_field, idx: int, wdat: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, path: pyuvm._reg.uvm_reg_model.uvm_door_e, map: pyuvm._reg.uvm_reg_map.uvm_reg_map) → None

abstractmethod async post_write(field: pyuvm._reg.uvm_vreg_field.uvm_vreg_field, idx: int, wdat: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, path: pyuvm._reg.uvm_reg_model.uvm_door_e, map: pyuvm._reg.uvm_reg_map.uvm_reg_map, status: pyuvm._reg.uvm_reg_model.uvm_status_e) → None

abstractmethod async pre_read(field: pyuvm._reg.uvm_vreg_field.uvm_vreg_field, idx: int, path: pyuvm._reg.uvm_reg_model.uvm_door_e, map: pyuvm._reg.uvm_reg_map.uvm_reg_map) → None

abstractmethod async post_read(field: pyuvm._reg.uvm_vreg_field.uvm_vreg_field, idx: int, rdat: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, path: pyuvm._reg.uvm_reg_model.uvm_door_e, map: pyuvm._reg.uvm_reg_map.uvm_reg_map, status: pyuvm._reg.uvm_reg_model.uvm_status_e) → None

class pyuvm.uvm_vreg_field_cb(name: str = 'uvm_callbacks'): Bases: pyuvm._s10_synchronization_classes.uvm_callbacks

class pyuvm.uvm_vreg_field_cb_iter(obj: type[pyuvm._s05_base_classes.uvm_object] | pyuvm._s05_base_classes.uvm_object)

Bases: pyuvm._s10_synchronization_classes.uvm_callback_iter

Initialization

class pyuvm.uvm_object(name='')

The most basic UVM object

Initialization

:param name: Name of the object. Default is empty string.

get_uvm_seeding(): Not implemented

set_uvm_seeding(enable): Not implemented

reseed(): Not implemented

get_name()

:return: String with name of uvm_object.

Return the name of this object as passed by the constructor

set_name(name)

:param name: Name of the object

Set the name

get_full_name()

:return: The full path and name of the object

The full name for a uvm_object is simply the name

get_inst_id(): :return: The python ID which fits the bill for what the ID is supposed to be.

get_type(): Not implemented because Python can implement the factory without these shenanigans.

get_object_type(): Not implemented because Python can implement the factory without these shenanigans.

get_type_name(): :return: Returns the type’s __name__ magic variable

classmethod create(name): :return: new object from factory

clone(): :return: A new object with the same name and data as this object.

print(): Not implemented. Use str() and print()

sprint(): Not implemented. use str() and print()

do_print(): not implemented. Use str() and print()

convert2string()

:return: The result of __str__()

Override if you want something different than __str__()

record(): Not implemented.

do_record(): Not implemented as we are not in a simulator

copy(rhs)

:param rhs: The object to copy from :return: None

Copy fields from rhs to this object using self.do_copy()

do_copy(rhs)

:param rhs: The object to copy from :return: None

By default we copy the name. Override this function to copy the rest of the object members.

compare(rhs)

:param rhs: The object being compared. :returns: True if do_compare() believes the objects are the same.

Compares one uvm_object to another uvm_object using the user-overridden do_compare() function.

do_compare(rhs)

:param rhs: The object being compared. :returns: True if the objects are the same.

Uses __eq__() to compare the objects. Override this to change the compare behavior.

pack(): Not implemented. There are Pythonic solutions to this.

pack_bytes(): Not implemented. There are Pythonic solutions to this.

pack_ints(): Not implemented. There are Pythonic solutions to this.

pack_longints(): Not implemented. There are Pythonic solutions to this.

do_pack(): Not implemented. There are Pythonic solutions to this.

unpack(): Not implemented. There are Pythonic solutions to this.

push_active_policy(): Not implemented.

pop_active_policy(): Not implemented.

get_active_policy(): Not implemented.

unpack_bytes(): Not implemented. There are Pythonic solutions to this.

unpack_ints(): Not implemented. There are Pythonic solutions to this.

unpack_longints(): Not implemented. There are Pythonic solutions to this.

do_unpack(): Not implemented. There are Pythonic solutions to this.

set_local(): Not implemented use Python getattr and setattr.

do_execute_op(op): Not implemented.

class pyuvm.uvm_field_op

We do not implement the UVM field op as this is a UVM way of providing field-based functionality that can better be implemented using Python functionality.

__new__(*args, **kwargs)

class pyuvm.uvm_policy

The uvm_policy is used to add functionality to SystemVerilog that already exists in Python. It is not needed in pyuvm.

__new__(*args, **kwargs)

class pyuvm.uvm_transaction(name='', initiator=None)

Transactions without interface to logging or waveforms.

Initialization

:param name: Object name :param initiator: component that is the initiator

set_id_info(other)

:param other: uvm_transaction with transaction_id :return: None

Set transaction_id from other

set_initiator(initiator)

:param initiator: initiator to set :return: None

5.4.2.14

get_initiator()

:return: initiator

5.4.2.15

__not_implemented()

accept_tr(accept_time=0)

:param accept_time: Simulation time when the transaction is accepted

IEEE 1800.2 5.4.2.2

do_accept_tr(): User definable method to add to accept_tr()

begin_tr(begin_time=0, parent_handle=None) → int: :param begin_time: Simulation time at which the transaction is acted upon by the driver :param parent_handle:

do_begin_tr(): User definable method

end_tr(end_time=0, free_handle=True) → None: :param end_time: Simulation time at which the transaction is marked as acted upon :param free_handle: :return: None

do_end_tr(): Not implemented

get_tr_handle(): Not implemented

enable_recording(): Not implemented

disable_recording(): Not implemented

is_recording_enabled(): Not implemented

is_active(): Not implemented

get_event_pool(): Not implemented

get_accept_time() → int: :return: Accept time of transaction

get_begin_time() → int: :return: Begin time of transaction

get_end_time() → int: :return: End time of transaction

set_transaction_id(txn_id)

:param txn_id: Transaction ID

Sets transaction’s transaction_id

get_transaction_id()

:return: Transaction ID

Returns transaction_id

class pyuvm.uvm_report_object(name)

__default_logging_level

None

The basis of all classes that can report

get_initial_logger_name()

:returns: The name of the initial logger

Override this method if you want to change the way the logger name is generated.

The default looks like this:

.. code-block:: python return self.get_full_name() + str(id(self))

static set_default_logging_level(default_logging_level): :param default_logging_level: The default logging level :returns: None

static get_default_logging_level(): :returns: The default logging level

set_logging_level(logging_level): :param logging_level: The logging level :returns: None

add_logging_handler(handler): :param handler: The logging handler :returns: None

remove_logging_handler(handler): :param handler: The logging handler to remove :returns: None

remove_streaming_handler()

:returns: None

Removes the streaming handler

disable_logging()

:returns: None

Disables logging

class pyuvm.uvm_factory

The uvm_factory is a singleton that delivers all UVM factory functions.

Initialization

clear_all(): Clear all the classes and overrides from the factory

clear_overrides(): Clear all the overrides from the factory

__set_override(original, override, path=None)

set_inst_override_by_type(original_type, override_type, full_inst_path)

:param original_type: The original type being overridden :param override_type: The overriding type :param full_inst_path: The inst where this happens :return: None

Override an instance with a new type if original type is at that path

set_inst_override_by_name(original_type_name, override_type_name, full_inst_path)

:param original_type_name: the name of type being replaced :param override_type_name: the name of the substitute type :param full_inst_path: The path to the instance :return: None

Override a specific instance using strings that contain the names of the types.

set_type_override_by_type(original_type, override_type, replace=True)

:param original_type: The original type to be overridden :param override_type: The new type that will override it :param replace: If the override exists, only replace it if this is True :return: None

Override one type with another type globally

set_type_override_by_name(original_type_name, override_type_name, replace=True)

:param original_type_name: The name of the type to be overridden or an arbitrary string. :param override_type_name: The name of the overriding type. It must have been declared. :param replace: If the override already exists only replace if this is True

Override one type with another type globally using strings containing the type names.

__find_override(requested_type, parent_inst_path='', name='')

create_object_by_type(requested_type, parent_inst_path='', name='')

:param requested_type: The type that we request but that can be overridden :param parent_inst_path: The get_full_name path of the parent :param name: The name of the instance requested_type(“name”) :raises: UVMFactoryError if the type is not in the factory :return: Type that is child of uvm_object.

8.3.1.5 Creation If the type is is not in the factory we raise UVMFactoryError

create_object_by_name(requested_type_name, parent_inst_path='', name='')

:param requested_type_name: the type that could be overridden :param parent_inst_path: A path if we are checking for inst overrides :param name: The name of the new object. :raises: UVMFactoryError if the type is not in the factory :return: A uvm_object with the name given

Create an object using a string to define its uvm_object type.

create_component_by_type(requested_type, parent_inst_path='', name='', parent=None)

:param requested_type: Type type to be overridden :param parent_inst_path: The inst path if we are looking for inst overrides :param name: Concatenated with parent_inst_path if it exists for inst overrides :param parent: The parent component :raises: UVMFactoryError if the type is not in the factory :return: a uvm_component with the name an parent given.

Create a component of the requested uvm_component type. If the type is is not in the factory we raise UVMFactoryError

create_component_by_name(requested_type_name, parent_inst_path='', name='', parent=None)

Create a components using the name of the requested uvm_component type

:param requested_type_name: the type that could be overridden :param parent_inst_path: A path if we are checking for inst overrides :param name: The name of the new object. :param parent: The component’s parent component :raises: UVMFactoryError if the type is not in the factory :return: A uvm_object with the name given

set_type_alias(alias_type_name, original_type): :param alias_type_name:A string that will reference the original type :param original_type:The original type toe be referenced :raises: UVMNotImplemented Not implemented as it does not seem to exist in the SystemVerilog UVM :return:None

set_inst_alias(alias_type_name, original_type, full_inst_path): :param alias_type_name:A string that will reference the original type :param original_type:The original type toe be referenced :param full_inst_path: The instance path where this alias is active :raises: UVMNotImplemented Not implemented as it does not seem to exist in SystemVerilog UVM :return:None

find_override_by_type(requested_type, full_inst_path)

:param requested_type: The type whose override you want :param full_inst_path: The inst path where one looks :raises: UVMFactoryError if the type is not in the factory :return: class object

Given a type and instance path, return the override class object.

find_override_by_name(requested_type_name, full_inst_path)

:param requested_type_name: :param full_inst_path: :raises: UVMFactoryError if the type is not in the factory :return: class object

Given a path and the name of a class return its overriding class object

find_wrapper_by_name(): :raises: UVMNotImplemented There are no wrappers in pyuvm so this is not implemented.

is_type_name_registered(type_name)

:param type_name: string that is name of a type :return: boolean True if type is registered

Checks that a type of this name is registered with the factory.

is_type_registered(uvm_type)

:param uvm_type: The type to be checked :return: boolean True if type is registered

Checks that a type is registered. The argument is named “obj” in the spec, but that name is ridiculous and confusing.

property debug_level

uvm_factory().debug_level = 0 : overrides
uvm_factory().debug_level = 1 : user defined types + above
uvm_factory().debug_level = 2 : uvm_* types + above

__str__()

Returns the Pythonic string Set uvm_factory().debug_level to a value to control the string. The default is 1

uvm_factory().debug_level = 0 : overrides uvm_factory().debug_level = 1 : user defined types + above uvm_factory().debug_level = 2 : uvm_* types + above

:return: String containing factory data

print(debug_level=1)

:param debug_level: * debug_level = 0 : overrides * debug_level = 1 : user defined types + above ( default) * debug_level = 2 : uvm_* types + above :return: None

Prints the factory data using debug_level to control the amount of output. The uvm_factory().debug_level variable can control this for str()

class pyuvm.uvm_phase(name='')

classmethod execute(comp): :param comp: The component whose turn it is to execute

__str__()

class pyuvm.uvm_topdown_phase(name='')

Bases: pyuvm._s09_phasing.uvm_phase

Runs phases from the top down.

Initialization

:param name: Name of the object. Default is empty string.

classmethod traverse(comp)

:param comp: The component whose hierarchy will be traversed

Given a component, we traverse the component tree top to bottom calling the phase functions as we go

class pyuvm.uvm_bottomup_phase(name='')

Bases: pyuvm._s09_phasing.uvm_phase

Runs the phases from bottom up.

Initialization

:param name: Name of the object. Default is empty string.

classmethod traverse(comp)

:param comp: The component whose hierarchy will be traversed

Given a component, we traverse the component tree bottom to top calling the phase functions as we go

class pyuvm.uvm_threaded_execute_phase(name='')

Bases: pyuvm._s09_phasing.uvm_phase

This phase launches the phase function in a thread and returns the thread to the caller. The caller can then join all the threads.

Initialization

:param name: Name of the object. Default is empty string.

classmethod execute(comp)

class pyuvm.uvm_build_phase(name=''): Bases: pyuvm._s09_phasing.uvm_topdown_phase

class pyuvm.uvm_connect_phase(name=''): Bases: pyuvm._s09_phasing.uvm_bottomup_phase

class pyuvm.uvm_end_of_elaboration_phase(name=''): Bases: pyuvm._s09_phasing.uvm_topdown_phase

class pyuvm.uvm_start_of_simulation_phase(name=''): Bases: pyuvm._s09_phasing.uvm_topdown_phase

class pyuvm.uvm_run_phase(name=''): Bases: pyuvm._s09_phasing.uvm_threaded_execute_phase, pyuvm._s09_phasing.uvm_bottomup_phase

class pyuvm.uvm_extract_phase(name=''): Bases: pyuvm._s09_phasing.uvm_topdown_phase

class pyuvm.uvm_check_phase(name=''): Bases: pyuvm._s09_phasing.uvm_topdown_phase

class pyuvm.uvm_report_phase(name=''): Bases: pyuvm._s09_phasing.uvm_topdown_phase

class pyuvm.uvm_final_phase(name=''): Bases: pyuvm._s09_phasing.uvm_topdown_phase

pyuvm.uvm_common_phases: None

class pyuvm.uvm_callback(name: str = 'uvm_callback')

callback_mode(on: bool | None = None)

is_enabled() → bool

class pyuvm.uvm_callbacks(name: str = 'uvm_callbacks')

_instance: None

_callbacks: dict[pyuvm._s05_base_classes.uvm_object | type, list[pyuvm._s10_synchronization_classes.uvm_callback]]: None

__new__(*args, **kwargs)

classmethod get()

classmethod add(obj, cb, ordering: pyuvm._s10_synchronization_classes.uvm_apprepend = uvm_apprepend.UVM_APPEND)

classmethod add_by_name(name: str, cb: pyuvm._s10_synchronization_classes.uvm_callback, root: pyuvm._s13_predefined_component_classes.uvm_component, ordering: pyuvm._s10_synchronization_classes.uvm_apprepend = uvm_apprepend.UVM_APPEND) → None

classmethod delete(obj, cb: pyuvm._s10_synchronization_classes.uvm_callback) → None

classmethod delete_by_name(name: str, cb: pyuvm._s10_synchronization_classes.uvm_callback, root: pyuvm._s13_predefined_component_classes.uvm_component)

abstractmethod classmethod get_first(itr: int, obj: pyuvm._s05_base_classes.uvm_object) → pyuvm._s10_synchronization_classes.uvm_callback | None

abstractmethod classmethod get_last(itr: int, obj: pyuvm._s05_base_classes.uvm_object) → pyuvm._s10_synchronization_classes.uvm_callback | None

abstractmethod classmethod get_next(itr: int, obj: pyuvm._s05_base_classes.uvm_object) → pyuvm._s10_synchronization_classes.uvm_callback | None

abstractmethod classmethod get_prev(itr: int, obj: pyuvm._s05_base_classes.uvm_object) → pyuvm._s10_synchronization_classes.uvm_callback | None

abstractmethod classmethod get_all(obj: pyuvm._s05_base_classes.uvm_object) → list[pyuvm._s10_synchronization_classes.uvm_callback]

class pyuvm.uvm_callback_iter(obj: type[pyuvm._s05_base_classes.uvm_object] | pyuvm._s05_base_classes.uvm_object)

Initialization

__iter__()

__next__() → pyuvm._s10_synchronization_classes.uvm_callback

next() → pyuvm._s10_synchronization_classes.uvm_callback | None

prev() → pyuvm._s10_synchronization_classes.uvm_callback | None

first() → pyuvm._s10_synchronization_classes.uvm_callback | None

last() → pyuvm._s10_synchronization_classes.uvm_callback | None

get_cb() → pyuvm._s10_synchronization_classes.uvm_callback | None

class pyuvm.uvm_export_base(name, parent): Bases: pyuvm._s13_uvm_component.uvm_component

class pyuvm.uvm_port_base(name, parent)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_export_base

A uvm_port_base is a uvm_component with a connect() function. The connect function creates an __export data member that implements the put/get,etc methods.

We’ll build functionality from uvm_port_base to create the other combinations of ports through multiple inheritance.

pyuvm will make extensive use of Pythons “ask forgiveness” policy If you try to use the wrong method for the port you created then you’ll get a exception, maybe a missing attribute exception, though we could catch that one and deliver a more useful message.

Unlike the SV implementation of UVM we return results from get and peek as function call returns. This is more pythonic.

Initialization

13.1.2.1—This is new() in the IEEE-UVM, but we mean the same thing with init()

:param name: The name of the component. Used in the UVM hierarchy :param parent: The parent component. If None, the parent is uvm_root

__tlm_method_list: [‘put’, ‘get’, ‘peek’, ‘try_put’, ‘try_get’, ‘try_peek’, ‘can_put’, ‘can_get’, ‘can_peek’, ‘transpor…

_check_export(export): Check that the export implements needed methods

connect(export)

:param export: The export that has the functions :raises: UVMTLMConnectionError if there is a connect error :return: None

Attach this port to the associated export.

class pyuvm.uvm_blocking_put_port(name, parent)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_port_base

Access the blocking put interfaces

Initialization

13.1.2.1—This is new() in the IEEE-UVM, but we mean the same thing with init()

:param name: The name of the component. Used in the UVM hierarchy :param parent: The parent component. If None, the parent is uvm_root

async put(datum)

:param datum: Datum to put
:raises: UVMTLMConnectionError if export is missing
:return: None

put the datum

class pyuvm.uvm_nonblocking_put_port(name, parent)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_port_base

Access the non_blocking put interface

Initialization

13.1.2.1—This is new() in the IEEE-UVM, but we mean the same thing with init()

:param name: The name of the component. Used in the UVM hierarchy :param parent: The parent component. If None, the parent is uvm_root

try_put(data)

:param data: data to deliver :raises: UVMTLMConnectionError if export is missing :return: boolean True = success

Tries to put data on a port, but if the port is full it returns False

can_put()

Returns true if there is room for data to be put on the port

:return: True if there is room to put

class pyuvm.uvm_put_port(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_put_port, pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_put_port

class pyuvm.uvm_blocking_get_port(name, parent)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_port_base

Access the blocking get export methods

Initialization

13.1.2.1—This is new() in the IEEE-UVM, but we mean the same thing with init()

:param name: The name of the component. Used in the UVM hierarchy :param parent: The parent component. If None, the parent is uvm_root

async get()

:raises: UVMTLMConnectionError if export is missing :return: data

A blocking get that returns the data got

class pyuvm.uvm_nonblocking_get_port(name, parent)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_port_base

Access the non_blocking methods in export

Initialization

13.1.2.1—This is new() in the IEEE-UVM, but we mean the same thing with init()

:param name: The name of the component. Used in the UVM hierarchy :param parent: The parent component. If None, the parent is uvm_root

try_get()

:raises: UVMTLMConnectionError if export is missing :return: (success, data)

12.2.4.2.6 Returns a tuple containing success and the data This is different than SV UVM that returns the data through the argument list. :return: (success, data)

can_get(): :raises: UVMTLMConnectionError if export is missing :return: bool Returns true if there is data to get

class pyuvm.uvm_get_port(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_get_port, pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_get_port

class pyuvm.uvm_blocking_peek_port(name, parent)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_port_base

Provides access to the peek methods

Initialization

13.1.2.1—This is new() in the IEEE-UVM, but we mean the same thing with init()

:param name: The name of the component. Used in the UVM hierarchy :param parent: The parent component. If None, the parent is uvm_root

async peek()

:raises: UVMTLMConnectionError if export is missing :return: datum

A blocking peek that returns data without consuming it.

class pyuvm.uvm_nonblocking_peek_port(name, parent)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_port_base

Try a peek

Initialization

13.1.2.1—This is new() in the IEEE-UVM, but we mean the same thing with init()

:param name: The name of the component. Used in the UVM hierarchy :param parent: The parent component. If None, the parent is uvm_root

try_peek()

:raises: UVMTLMConnectionError if export is missing :return: (success, data)

Tries to peek for data and returns a tuple with success and the data

can_peek()

:raises: UVMTLMConnectionError if export is missing :return: True if can peek

Checks if peeking will be successful

class pyuvm.uvm_peek_port(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_peek_port, pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_peek_port

class pyuvm.uvm_blocking_get_peek_port(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_get_port, pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_peek_port

class pyuvm.uvm_nonblocking_get_peek_port(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_get_port, pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_peek_port

class pyuvm.uvm_get_peek_port(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_get_peek_port, pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_get_peek_port

class pyuvm.uvm_blocking_transport_port(name, parent)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_port_base

async transport(put_data)

Puts data and blocks if there is no room, then blocks if there is no data to get and gets data.

:param put_data: data to send :raises: UVMTLMConnectionError if export is missing :return: data received

class pyuvm.uvm_nonblocking_transport_port(name, parent)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_port_base

nb_transport(put_data)

Non-blocking transport. Returns a tuple with success if the transport was successful and the data could be returned

:param put_data: data to send :raises: UVMTLMConnectionError if export is missing :return: (success, data)

class pyuvm.uvm_transport_port(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_transport_port, pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_transport_port

class pyuvm.uvm_blocking_master_port(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_put_port, pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_get_peek_port

class pyuvm.uvm_nonblocking_master_port(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_put_port, pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_get_peek_port

class pyuvm.uvm_master_port(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_master_port, pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_master_port

class pyuvm.uvm_blocking_slave_port(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_put_port, pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_get_peek_port

class pyuvm.uvm_nonblocking_slave_port(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_get_peek_port, pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_put_port

class pyuvm.uvm_slave_port(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_slave_port, pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_slave_port

class pyuvm.uvm_analysis_imp(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_port_base

class pyuvm.uvm_analysis_port(name, parent)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_port_base

write(datum)

Write to all connected analysis ports. This is a broadcast. Returns regardless of whether there are any subscribers.

:param datum: data to send :raises: UVMTLMConnectionError if export is missing :return: None

connect(export)

class pyuvm.uvm_nonblocking_put_export(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_export_base

class pyuvm.uvm_blocking_put_export(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_export_base

class pyuvm.uvm_put_export(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_put_export, pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_put_export

class pyuvm.uvm_nonblocking_get_export(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_export_base

class pyuvm.uvm_blocking_get_export(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_export_base

class pyuvm.uvm_get_export(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_get_export, pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_get_export

class pyuvm.uvm_nonblocking_peek_export(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_export_base

class pyuvm.uvm_blocking_peek_export(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_export_base

class pyuvm.uvm_peek_export(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_peek_export, pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_peek_export

class pyuvm.uvm_blocking_get_peek_export(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_export_base

class pyuvm.uvm_nonblocking_get_peek_export(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_export_base

class pyuvm.uvm_get_peek_export(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_get_peek_export, pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_get_peek_export

class pyuvm.uvm_blocking_transport_export(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_export_base

class pyuvm.uvm_nonblocking_transport_export(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_export_base

class pyuvm.uvm_transport_export(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_transport_export, pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_transport_export

class pyuvm.uvm_blocking_master_export(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_put_export, pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_get_peek_export

class pyuvm.uvm_nonblocking_master_export(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_peek_export, pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_get_peek_export

class pyuvm.uvm_master_export(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_master_export, pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_master_export

class pyuvm.uvm_blocking_slave_export(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_put_export, pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_get_peek_export

class pyuvm.uvm_nonblocking_slave_export(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_put_export, pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_get_peek_export

class pyuvm.uvm_slave_export(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_slave_export, pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_slave_export

class pyuvm.uvm_analysis_export(name, parent): Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_export_base

class pyuvm.uvm_tlm_fifo_base(name, parent, maxsize=1)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_QueueAccessor, pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_put_export

Declares and instantiate the exports needed to communicate through the Queue.

Initialization

13.1.2.1—This is new() in the IEEE-UVM, but we mean the same thing with init()

:param name: The name of the component. Used in the UVM hierarchy :param parent: The parent component. If None, the parent is uvm_root

class uvm_BlockingPutExport(name, parent, uvm_queue, ap)

async put(item)

:param item: item to put :return: None

A coroutine that blocks if the FIFO is full.

class uvm_NonBlockingPutExport(name, parent, uvm_queue, ap)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_QueueAccessor, pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_put_export

can_put(): :return: True if can put

try_put(item)

:param item: item to put :raises: QueueFull if the queue is full :return: True if successful

The try_put is implemented with an exception rather than returning a boolean.

class uvm_PutExport(name, parent, uvm_queue, ap): Bases: uvm_BlockingPutExport, uvm_NonBlockingPutExport

class uvm_BlockingGetExport(name, parent, uvm_queue, ap)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_QueueAccessor, pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_get_export

async get()

:return: item

A coroutine that blocks if the FIFO is empty

class uvm_NonBlockingGetExport(name, parent, uvm_queue, ap)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_QueueAccessor, pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_get_export

can_get(): :return: True if can get

try_get(): :return: (success, item)

class uvm_GetExport(name, parent, uvm_queue, ap): Bases: uvm_BlockingGetExport, uvm_NonBlockingGetExport

class uvm_BlockingPeekExport(name, parent, uvm_queue, ap)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_QueueAccessor, pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_peek_export

async peek()

:return: item

A coroutine that blocks if the FIFO is empty

class uvm_NonBlockingPeekExport(name, parent, uvm_queue, ap)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_QueueAccessor, pyuvm._s12_uvm_tlm_interfaces.uvm_nonblocking_peek_export

can_peek(): :return: True if can peek

try_peek(): :return: (success, item)

class uvm_PeekExport(name, parent, uvm_queue, ap): Bases: uvm_BlockingPeekExport, uvm_NonBlockingPeekExport

class uvm_BlockingGetPeekExport(name, parent, uvm_queue, ap): Bases: uvm_BlockingGetExport, uvm_BlockingPeekExport

class uvm_NonBlockingGetPeekExport(name, parent, uvm_queue, ap): Bases: uvm_NonBlockingGetExport, uvm_NonBlockingPeekExport

class uvm_GetPeekExport(name, parent, uvm_queue, ap): Bases: uvm_GetExport, uvm_PeekExport

async put(item)

:param item: item to put

Blocking put coroutine

can_put(): :return: True if can put

try_put(item): :param item: item to put :return: True if successful

async get()

:return: item

coroutine that blocks if FIFO is empty

can_get(): :return: True if can get

try_get(): :return: (success, item)

async peek()

:return: item

A coroutine that blocks if FIFO is empty

can_peek(): :return: True if can peek

try_peek(): :return: (success, item)

class pyuvm.uvm_tlm_fifo(name=None, parent=None, size=1)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_tlm_fifo_base

size()

:return: size of FIFO

Return the size of the fifo

used()

:return: Number of items in the FIFO

How much of the FIFO is being used?

is_empty()

Returns true if FIFO is empty

:return: True if empty

is_full()

Test for full FIFO

:return: True if full

flush(): Flush out the FIFO

class pyuvm.uvm_tlm_analysis_fifo(name, parent=None)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_tlm_fifo

class uvm_AnalysisExport(name, parent, uvm_queue, ap)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_QueueAccessor, pyuvm._s12_uvm_tlm_interfaces.uvm_analysis_port

write(item)

:param item: item to write

Writes the item to all the subscribers, or no one if there are no subscribers.

class pyuvm.uvm_tlm_req_rsp_channel(name, parent=None, request_fifo_size=1, response_fifo_size=1)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_master_port, pyuvm._s12_uvm_tlm_interfaces.uvm_get_peek_port

class uvm_MasterSlaveExport(name, parent, put_export, get_peek_export)

async put(item)

:param item: item to put

A coroutine that blocks if the FIFO is full

can_put(): :return: True if can put

try_put(item): :param item: item to put :return: True if successful

async get()

:return: item

A coroutine that blocks if the FIFO is empty

can_get(): :return: True if can get

try_get(): :return: (success, item)

connect_phase()

class pyuvm.uvm_tlm_transport_channel(name, parent=None)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_tlm_req_rsp_channel

class uvm_TransportExport(name, parent, req_fifo, rsp_fifo)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_transport_port

async transport(req)

nb_transport(req)

class pyuvm.uvm_active_passive_enum

Bases: enum.IntEnum

UVM_PASSIVE: 0

UVM_ACTIVE: 1

class pyuvm.uvm_test(name, parent)

The base class for all tests

Initialization

13.1.2.1—This is new() in the IEEE-UVM, but we mean the same thing with init()

:param name: The name of the component. Used in the UVM hierarchy :param parent: The parent component. If None, the parent is uvm_root

class pyuvm.uvm_env(name, parent)

The base class for hierarchical containers of other components that together comprise a complete environment. The environment may initially consist of the entire testbench. Later, it can be reused as a sub-environment in even larger system-level environments.

Initialization

13.1.2.1—This is new() in the IEEE-UVM, but we mean the same thing with init()

:param name: The name of the component. Used in the UVM hierarchy :param parent: The parent component. If None, the parent is uvm_root

class pyuvm.uvm_agent(name, parent)

The :class:!uvm_agent virtual class should be used as the base class for the user-defined agents. Deriving from :class:!uvm_agent will allow you to distinguish agents from other component types also using its inheritance. Such agents will automatically inherit features that may be added to :class:!uvm_agent in the future.

While an agent’s build function, inherited from :class:~uvm_component, can be implemented to define any agent topology, an agent typically contains three subcomponents: a driver, sequencer, and monitor. If the agent is active, subtypes should contain all three subcomponents. If the agent is passive, subtypes should contain only the monitor.

Initialization

13.1.2.1—This is new() in the IEEE-UVM, but we mean the same thing with init()

:param name: The name of the component. Used in the UVM hierarchy :param parent: The parent component. If None, the parent is uvm_root

build_phase(): This build_phase() implements agent-specific behavior. * It sets the agent’s is_active property to UVM_ACTIVE * It allows the user to override the is_active property using the cdb_get() method. * It logs a warning if the user sets an illegal value for is_active and sets the value to UVM_ACTIVE.

get_is_active(): Returns :data:~uvm_active_passive_enum.UVM_ACTIVE if the agent is acting as an active agent and :data:~uvm_active_passive_enum.UVM_PASSIVE if it is acting as a passive agent. The default implementation is to just return the is_active flag, but the component developer may override this behavior if a more complex algorithm is needed to determine the active/passive nature of the agent.

active()

class pyuvm.uvm_monitor(name, parent)

This class should be used as the base class for user-defined monitors.

Deriving from :class:!uvm_monitor allows you to distinguish monitors from generic component types inheriting from :class:~uvm_component. Such monitors will automatically inherit features that may be added to :class:!uvm_monitor in the future.

Initialization

13.1.2.1—This is new() in the IEEE-UVM, but we mean the same thing with init()

:param name: The name of the component. Used in the UVM hierarchy :param parent: The parent component. If None, the parent is uvm_root

class pyuvm.uvm_scoreboard(name, parent)

This class should be used as the base class for user-defined scoreboards.

Deriving from :class:!uvm_scoreboard will allow you to distinguish scoreboards from other component types inheriting directly from :class:~uvm_component. Such scoreboards will automatically inherit and benefit from features that may be added to :class:!uvm_scoreboard in the future.

Initialization

13.1.2.1—This is new() in the IEEE-UVM, but we mean the same thing with init()

:param name: The name of the component. Used in the UVM hierarchy :param parent: The parent component. If None, the parent is uvm_root

class pyuvm.uvm_driver(name, parent)

The base class for drivers that initiate requests for new transactions via a :class:~uvm_seq_item_pull_port. The ports are typically connected to the exports of an appropriate sequencer component.

This driver operates in pull mode. Its ports are typically connected to the corresponding exports in a pull sequencer as follows:

.. code-block:: python

driver.seq_item_port.connect(sequencer.seq_item_export)
driver.rsp_port.connect(sequencer.rsp_export)

The rsp_port needs connecting only if the driver will use it to write responses to the analysis export in the sequencer.

Initialization

Creates and initializes an instance of this class using the normal constructor arguments for :class:~uvm_component: name is the name of the instance, and parent is the handle to the hierarchical parent, if any.

class pyuvm.uvm_subscriber(name, parent)

This class provides an analysis export for receiving transactions from a connected analysis export. Making such a connection “subscribes” this component to any transactions emitted by the connected analysis port.

Subtypes of this class must define the write method to process the incoming transactions. This class is particularly useful when designing a coverage collector that attaches to a monitor.

Initialization

13.1.2.1—This is new() in the IEEE-UVM, but we mean the same thing with init()

:param name: The name of the component. Used in the UVM hierarchy :param parent: The parent component. If None, the parent is uvm_root

class uvm_AnalysisImp(name, parent, write_fn)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_analysis_export

write(tt)

Write a transaction to all the connected subscribers.

:param tt: The transaction to write :return: None

write(tt): Method that must be defined in each subclass. Access to this method by outside components should be done via the :any:analysis_export.

class pyuvm.uvm_component(name, parent)

Bases: pyuvm._s06_reporting_classes.uvm_report_object

component_dict: None

classmethod clear_components()

clear_children(): Removes the direct children from this component.

clear_hierarchy(): Removes self from the UVM hierarchy

do_execute_op(op)

classmethod create(name='', parent=None)

get_parent()

:return: parent object

13.1.3.1

raise_objection(description='', stacklevel=1)

Raise an objection, usually at the start of the run_phase()

:param str description: A meaningful description speeds up timeout debug :param int stacklevel: For debug, increase to associate with higher level caller

drop_objection(description='')

Drop an objection, usually at the end of the run_phase()

:param str description: Not used, but kept for symmetry with raise_objection

objection()

cdb_set(label, value, inst_path='*')

A convenience routing to store an object in the config_db using this component’s get_full_name() path.

:param value: The object to store :param label: The label to use to retrieve it :param inst_path: A path with globs or if left blank the get_full_name() path

cdb_get(label, inst_path='')

A convenience routine that retrieves an object from the config_db using this component’s get_full_name() path. Can find objects stored with wildcards

:param inst_path: The path below this component :param label: The label used to store the value :return: The object at this path stored at the label

property parent

get_full_name()

:return: This component’s name concatenated to parent name.

13.1.3.2

get_children(): 13.1.3.3 :return: A dict containing children objects

add_child(name, child)

property hierarchy

We return a generator to find the children. This is more pythonic and saves memory for large hierarchies.

:return: A generator that returns the children.

property children: 13.1.3.4 Implements the intention of this requirement without the approach taken in the UVM We use a generator instead.

__repr__()

get_child(name): 13.1.3.4 :param self: :param name: child’s name :return: child uvm_component of that name

get_num_children(): 13.1.3.5 :param self: :return: The number of children in component

has_child(name): 13.1.3.6 :param name: Name of child the object :return: True if exists, False otherwise

lookup(name)

13.1.3.7 Return a component base on the path. If . then use full name from root otherwise relative

:param name: The search name :return: either the component or None

get_depth()

13.1.3.8 Get the depth that I am from the top component. uvm_root is 0.

:return: The hierarchy depth from me to the bottom.

set_logging_level_hier(logging_level)

Set the logging level for this component’s logger and all the way down the hierarchy

:param logging_level: typically a constant from logging module :return: None

add_logging_handler_hier(handler)

Add an additional handler all the way down the component hierarchy

:param handler: A logging.Handler object :return: None

remove_logging_handler_hier(handler)

Remove a handler from all loggers below this component

:param handler: logging handler :return: None

remove_streaming_handler_hier(): Remove this component’s streaming handler and all the way down the hierarchy

disable_logging_hier(): Disable logging for this component and all the way down the hierarchy

build_phase()

connect_phase()

end_of_elaboration_phase()

start_of_simulation_phase()

async run_phase()

extract_phase()

check_phase()

report_phase()

final_phase()

class pyuvm.uvm_root

F.7. We do not use uvm_pkg to hold uvm_root. Instead it is a class variable of uvm_component. This avoids circular reference issues regarding uvm_pkg.

Plus, it’s cleaner.

uvm_root is still a singleton that you access through its constructor instead of through a get() method.

Much of the functionality in Annex F delivers functionality in SystemVerilog that is already built into Python. So we’re going to skip much of that Annex.

Initialization

13.1.2.1—This is new() in the IEEE-UVM, but we mean the same thing with init()

:param name: The name of the component. Used in the UVM hierarchy :param parent: The parent component. If None, the parent is uvm_root

classmethod clear_singletons(keep_set={}): Clear the singletons in the system. This is used for testing

_utt(): Used in testing

async run_test(test_name, keep_singletons=False, keep_set=set()): :param test_name: The uvm test name or test class :param keep_singletons: If True do not clear singletons (default False) :param keep_set: Set of singleton classes to keep if keep_singletons is False. Pass a list of singletons to set() :return: none

_find_all_recurse(comp_match, comp) → list[pyuvm._s13_uvm_component.uvm_component]: Recursively finds all components matching comp_match. Returns a list of matching uvm_component instances.

find_all(comp_match: str, comp: pyuvm._s13_uvm_component.uvm_component | None = None) → list[pyuvm._s13_uvm_component.uvm_component]: Returns a list of components matching a given comp_match string. Matches are determined using uvm_is_match (see F.3.3.1), with comp_match as expr, and the component’s full name (see 13.1.3.2) as str. If the comp argument is not None, the search begins from that component down; otherwise, all component instances are compared.

find(comp_match: str) → pyuvm._s13_uvm_component.uvm_component | None: find does a find_all with comp = None and returns the first element in the output list or None if there is an empty list.

class pyuvm.ConfigDB

Initialization

default_get: ‘object(…)’

default_precedence: 1000

legal_chars

None

A path-based singleton storage system

clear(): Reset the ConfigDB. Used for testing.

static _get_context_inst_name(context, inst_name)

Get the config_key from context and passed inst_name

:param context: uvm_component or None :param inst_name: string that can be a glob :return: string that is the key

_get_event_key(context, inst_name, field_name): Key for lookup events in dictionary

trace(method, context, inst_name, field_name, value): Output the ConfigDB activity if tracing is on.

set(context, inst_name, field_name, value)

Stores an object in the db using the context and inst_name to create a retrieval path, and the key name.

:param context: A handle to a component :param inst_name: The instance name within the component :param field_name: The key we’re setting :param value: The object to be stored :return: None

get(context, inst_name, field_name, default=default_get)

The component path matches against the paths in the ConfigDB. The path cannot have wildcards, but can match against keys with wildcards. Return the value stored at key. If the key is missing, returns default or raises UVMConfigItemNotFound.

:param context: The component making the call :param inst_name: component full path with no wildcards :param field_name: the field_name being retrieved :param default: the value to return if there is no key, defaults to default_get :raises UVMConfigItemNotFound: if the key is not found and the default is not set :return: value found at location

_not_found(msg, default)

exists(context, inst_name, field_name)

Returns true if there is data in the database at this location

:param context: None or uvm_component :param inst_name: instance name string in context :param field_name: key name for location :return: True if exists

async wait_modified(context, inst_name, field_name)

__str__()

class pyuvm.ResponseQueue(maxsize: int = 0)

Bases: pyuvm._s12_uvm_tlm_interfaces.UVMQueue

The ResponseQueue is a queue that can cherry-pick an item using an id number, or simply return the next item in the queue.

Initialization

put_nowait(item)

Extend the cocotb.queue.Queue.put_nowait method to set the put_event flag. This flag is used to signal that an item has been put in the queue so that get_response can be unblocked.

:param item: The item to put in the queue :raises QueueFull: If the queue is full

async get_response(txn_id=None)

A coroutine that will either get a response item with the given transaction_id, or return the next item in the queue.

:param txn_id: (Optional) The transaction ID of the response you want to pluck from the queue. :return: The response item

__str__()

class pyuvm.uvm_sequence_item(name)

Bases: pyuvm._s05_base_classes.uvm_transaction

The pyuvm uvm_sequence_item has events to implement start_item() and finish_item()

Initialization

:param name: Object name :param initiator: component that is the initiator

set_context(item)

Use this to link a new response transaction to the request transaction. rsp.set_context(req)

:param item: The request transaction :return: None

class pyuvm.uvm_seq_item_export(name, parent)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_blocking_put_export

The sequence item port with a request queue and a response queue.

Initialization

13.1.2.1—This is new() in the IEEE-UVM, but we mean the same thing with init()

:param name: The name of the component. Used in the UVM hierarchy :param parent: The parent component. If None, the parent is uvm_root

async put_req(item)

put request into request queue. Block if the queue is full.

:param item: request item :return: None

put_response(item)

Put response into response queue. Do not block.

:param item: response item :raise QueueFull: If the queue is full :return:

async get_next_item()

A couroutine that gets the next item out of the item queue and blocks if the queue is empty.

:return: item to process

item_done(rsp=None)

Signal that the item has been completed. If rsp is not None put it into the response queue.

:param rsp: (optional) item to put in response queue if not None

async get_response(transaction_id=None)

A couroutine that will block if there is no transaction available

If transaction_id is not None, block until a response with the transaction id becomes available.

:param transaction_id: The transaction ID of the response :return: The response item

class pyuvm.uvm_seq_item_port(name, parent)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_port_base

connect(export)

async put_req(item)

A coroutine that blocks until the request is put in the queue

:param item: The request item

put_response(item)

Put a response back in the queue. aka put_response

:param item: The response item :Raises UVMFatalError: If the item is not a subclass of uvm_sequence_item

async get_next_item()

A coroutine that get the next sequence item from the request queue and blocks if the queue is empty.

:return: The next sequence item

item_done(rsp=None)

Notify the driver that it can get the next sequence. If rsp is not None, put it in the response queue.

:param rsp: (optional) The response item :raise UVMFatalError: If rsp is not a subclass of uvm_sequence_item

async get_response(transaction_id=None)

A coroutine that will ither get a response item with the given transaction_id, or get the first response item in the queue. Otherwise it will block until a response is ready.

:param transaction_id: The transaction ID of the response you want :return: The response item

class pyuvm.uvm_sequencer(name, parent)

The uvm_sequencer arbitrates between multiple sequences that want to send items to driver (connected to seq_export) It exposes put_req, get_next_item, get_response from the export. The sequence will use these to coordinate items with the sequencer.

Initialization

13.1.2.1—This is new() in the IEEE-UVM, but we mean the same thing with init()

:param name: The name of the component. Used in the UVM hierarchy :param parent: The parent component. If None, the parent is uvm_root

async run_phase()

async start_item(item)

async finish_item(item)

async put_req(req)

async get_response(txn_id=None)

async get_next_item()

class pyuvm.uvm_sequencer_base(name=''): Bases: pyuvm._s05_base_classes.uvm_object

class pyuvm.uvm_sequence_base(name): Bases: pyuvm._s14_15_python_sequences.uvm_sequence_item

class pyuvm.uvm_sequence(name='uvm_sequence')