pyuvm._s13_predefined_component_classes

Module Contents

Classes

uvm_active_passive_enum
uvm_test	The base class for all tests
uvm_env	The base class for hierarchical containers of other components that together comprise a complete environment. The environment may initially consist of the entire testbench. Later, it can be reused as a sub-environment in even larger system-level environments.
uvm_agent	The :class:!uvm_agent virtual class should be used as the base class for the user-defined agents. Deriving from :class:!uvm_agent will allow you to distinguish agents from other component types also using its inheritance. Such agents will automatically inherit features that may be added to :class:!uvm_agent in the future.
uvm_monitor	This class should be used as the base class for user-defined monitors.
uvm_scoreboard	This class should be used as the base class for user-defined scoreboards.
uvm_driver	The base class for drivers that initiate requests for new transactions via a :class:~uvm_seq_item_pull_port. The ports are typically connected to the exports of an appropriate sequencer component.
uvm_subscriber	This class provides an analysis export for receiving transactions from a connected analysis export. Making such a connection “subscribes” this component to any transactions emitted by the connected analysis port.

API

class pyuvm._s13_predefined_component_classes.uvm_active_passive_enum

Bases: enum.IntEnum

UVM_PASSIVE

0

UVM_ACTIVE

1

class pyuvm._s13_predefined_component_classes.uvm_test(name, parent)

Bases: pyuvm._s13_uvm_component.uvm_component

The base class for all tests

Initialization

13.1.2.1—This is new() in the IEEE-UVM, but we mean the same thing with init()

:param name: The name of the component. Used in the UVM hierarchy :param parent: The parent component. If None, the parent is uvm_root

class pyuvm._s13_predefined_component_classes.uvm_env(name, parent)

Bases: pyuvm._s13_uvm_component.uvm_component

The base class for hierarchical containers of other components that together comprise a complete environment. The environment may initially consist of the entire testbench. Later, it can be reused as a sub-environment in even larger system-level environments.

Initialization

13.1.2.1—This is new() in the IEEE-UVM, but we mean the same thing with init()

:param name: The name of the component. Used in the UVM hierarchy :param parent: The parent component. If None, the parent is uvm_root

class pyuvm._s13_predefined_component_classes.uvm_agent(name, parent)

Bases: pyuvm._s13_uvm_component.uvm_component

The :class:!uvm_agent virtual class should be used as the base class for the user-defined agents. Deriving from :class:!uvm_agent will allow you to distinguish agents from other component types also using its inheritance. Such agents will automatically inherit features that may be added to :class:!uvm_agent in the future.

While an agent’s build function, inherited from :class:~uvm_component, can be implemented to define any agent topology, an agent typically contains three subcomponents: a driver, sequencer, and monitor. If the agent is active, subtypes should contain all three subcomponents. If the agent is passive, subtypes should contain only the monitor.

Initialization

13.1.2.1—This is new() in the IEEE-UVM, but we mean the same thing with init()

:param name: The name of the component. Used in the UVM hierarchy :param parent: The parent component. If None, the parent is uvm_root

build_phase()

This build_phase() implements agent-specific behavior. * It sets the agent’s is_active property to UVM_ACTIVE * It allows the user to override the is_active property using the cdb_get() method. * It logs a warning if the user sets an illegal value for is_active and sets the value to UVM_ACTIVE.

get_is_active()

Returns :data:~uvm_active_passive_enum.UVM_ACTIVE if the agent is acting as an active agent and :data:~uvm_active_passive_enum.UVM_PASSIVE if it is acting as a passive agent. The default implementation is to just return the is_active flag, but the component developer may override this behavior if a more complex algorithm is needed to determine the active/passive nature of the agent.

active()

class pyuvm._s13_predefined_component_classes.uvm_monitor(name, parent)

Bases: pyuvm._s13_uvm_component.uvm_component

This class should be used as the base class for user-defined monitors.

Deriving from :class:!uvm_monitor allows you to distinguish monitors from generic component types inheriting from :class:~uvm_component. Such monitors will automatically inherit features that may be added to :class:!uvm_monitor in the future.

Initialization

13.1.2.1—This is new() in the IEEE-UVM, but we mean the same thing with init()

:param name: The name of the component. Used in the UVM hierarchy :param parent: The parent component. If None, the parent is uvm_root

class pyuvm._s13_predefined_component_classes.uvm_scoreboard(name, parent)

Bases: pyuvm._s13_uvm_component.uvm_component

This class should be used as the base class for user-defined scoreboards.

Deriving from :class:!uvm_scoreboard will allow you to distinguish scoreboards from other component types inheriting directly from :class:~uvm_component. Such scoreboards will automatically inherit and benefit from features that may be added to :class:!uvm_scoreboard in the future.

Initialization

13.1.2.1—This is new() in the IEEE-UVM, but we mean the same thing with init()

:param name: The name of the component. Used in the UVM hierarchy :param parent: The parent component. If None, the parent is uvm_root

class pyuvm._s13_predefined_component_classes.uvm_driver(name, parent)

Bases: pyuvm._s13_uvm_component.uvm_component

The base class for drivers that initiate requests for new transactions via a :class:~uvm_seq_item_pull_port. The ports are typically connected to the exports of an appropriate sequencer component.

This driver operates in pull mode. Its ports are typically connected to the corresponding exports in a pull sequencer as follows:

.. code-block:: python

driver.seq_item_port.connect(sequencer.seq_item_export)
driver.rsp_port.connect(sequencer.rsp_export)

The rsp_port needs connecting only if the driver will use it to write responses to the analysis export in the sequencer.

Initialization

Creates and initializes an instance of this class using the normal constructor arguments for :class:~uvm_component: name is the name of the instance, and parent is the handle to the hierarchical parent, if any.

class pyuvm._s13_predefined_component_classes.uvm_subscriber(name, parent)

Bases: pyuvm._s13_uvm_component.uvm_component

This class provides an analysis export for receiving transactions from a connected analysis export. Making such a connection “subscribes” this component to any transactions emitted by the connected analysis port.

Subtypes of this class must define the write method to process the incoming transactions. This class is particularly useful when designing a coverage collector that attaches to a monitor.

Initialization

13.1.2.1—This is new() in the IEEE-UVM, but we mean the same thing with init()

:param name: The name of the component. Used in the UVM hierarchy :param parent: The parent component. If None, the parent is uvm_root

class uvm_AnalysisImp(name, parent, write_fn)

Bases: pyuvm._s12_uvm_tlm_interfaces.uvm_analysis_export

write(tt)

Write a transaction to all the connected subscribers.

:param tt: The transaction to write :return: None

write(tt)

Method that must be defined in each subclass. Access to this method by outside components should be done via the :any:analysis_export.