pyuvm._reg.uvm_mem

Module Contents

Classes

uvm_mem

Data

__all__
logger

API

pyuvm._reg.uvm_mem.__all__

[‘uvm_mem’]

pyuvm._reg.uvm_mem.logger

‘getLogger(…)’

class pyuvm._reg.uvm_mem.uvm_mem(name: str, size: int, n_bits: int, access: str = 'RW', has_coverage: int = uvm_coverage_model_e.UVM_NO_COVERAGE)

Bases: pyuvm._s05_base_classes.uvm_object

_max_size: ClassVar[int]

0

configure(parent: pyuvm._reg.uvm_reg_block.uvm_reg_block, hdl_path: str = '') → None

set_offset(map: pyuvm._reg.uvm_reg_map.uvm_reg_map, offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, unmapped: bool = False) → None

set_parent(parent: pyuvm._reg.uvm_reg_block.uvm_reg_block) → None

add_map(map: pyuvm._reg.uvm_reg_map.uvm_reg_map) → None

_lock_model() → None

abstractmethod _add_vreg(vreg: pyuvm._reg.uvm_vreg.uvm_vreg) → None

abstractmethod _delete_vreg(vreg: pyuvm._reg.uvm_vreg.uvm_vreg) → None

get_full_name() → str

get_parent() → pyuvm._reg.uvm_reg_block.uvm_reg_block

get_block() → pyuvm._reg.uvm_reg_block.uvm_reg_block

get_n_maps() → int

is_in_map(map: pyuvm._reg.uvm_reg_map.uvm_reg_map) → bool

get_maps(maps: list[pyuvm._reg.uvm_reg_map.uvm_reg_map]) → None

get_local_map(map: pyuvm._reg.uvm_reg_map.uvm_reg_map) → pyuvm._reg.uvm_reg_map.uvm_reg_map | None

get_default_map() → pyuvm._reg.uvm_reg_map.uvm_reg_map | None

get_rights(map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None) → str

get_access(map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None) → str

get_size() → int

get_n_bytes() → int

get_n_bits() → int

static get_max_size() → int

get_virtual_registers() → list[pyuvm._reg.uvm_vreg.uvm_vreg]

get_virtual_fields() → list[pyuvm._reg.uvm_vreg_field.uvm_vreg_field]

abstractmethod get_vreg(name: str) → pyuvm._reg.uvm_vreg.uvm_vreg

get_vreg_by_name(name: str) → pyuvm._reg.uvm_vreg.uvm_vreg | None

get_vfield_by_name(name: str) → pyuvm._reg.uvm_vreg_field.uvm_vreg_field | None

abstractmethod get_vreg_by_offset(offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None) → pyuvm._reg.uvm_vreg.uvm_vreg

abstractmethod get_offset(offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t = 0, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None) → pyuvm._reg.uvm_reg_model.uvm_reg_addr_t

get_address(offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t = 0, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None) → pyuvm._reg.uvm_reg_model.uvm_reg_addr_t

get_addresses(offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t = 0, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None) → tuple[int, list[pyuvm._reg.uvm_reg_model.uvm_reg_addr_t]]

abstractmethod async write(offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, value: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_DEFAULT_DOOR, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, prior: int = -1, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → pyuvm._reg.uvm_reg_model.uvm_status_e

abstractmethod async read(offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_DEFAULT_DOOR, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, prior: int = -1, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → tuple[pyuvm._reg.uvm_reg_model.uvm_status_e, pyuvm._reg.uvm_reg_model.uvm_reg_data_t]

abstractmethod async burst_write(offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, value: list[pyuvm._reg.uvm_reg_model.uvm_reg_data_t], path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_DEFAULT_DOOR, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, prior: int = -1, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → pyuvm._reg.uvm_reg_model.uvm_status_e

abstractmethod async burst_read(offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, value: list[pyuvm._reg.uvm_reg_model.uvm_reg_data_t], path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_DEFAULT_DOOR, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, prior: int = -1, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → pyuvm._reg.uvm_reg_model.uvm_status_e

abstractmethod async poke(offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, value: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, kind: str = '', parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → pyuvm._reg.uvm_reg_model.uvm_status_e

abstractmethod async peek(offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, kind: str = '', parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → tuple[pyuvm._reg.uvm_reg_model.uvm_status_e, pyuvm._reg.uvm_reg_model.uvm_reg_data_t]

abstractmethod _check_access(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → pyuvm._reg.uvm_reg_map.uvm_reg_map_info | None

abstractmethod async do_write(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

abstractmethod async do_read(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

abstractmethod set_frontdoor(ftdr: pyuvm._reg.uvm_reg_sequence.uvm_reg_frontdoor, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, fname: str = '', lineno: int = 0) → None

abstractmethod get_frontdoor(map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None) → pyuvm._reg.uvm_reg_sequence.uvm_reg_frontdoor

abstractmethod set_backdoor(bkdr: pyuvm._reg.uvm_reg_backdoor.uvm_reg_backdoor, fname: str = '', lineno: int = 0) → None

abstractmethod get_backdoor(inherited: bool = True) → pyuvm._reg.uvm_reg_backdoor.uvm_reg_backdoor

abstractmethod clear_hdl_path(kind: str = 'RTL') → None

abstractmethod add_hdl_path(slices: list[pyuvm._reg.uvm_reg_model.uvm_hdl_path_slice], kind: str = 'RTL') → None

abstractmethod add_hdl_path_slice(name: str, offset: int, size: int, first: bool = False, kind: str = 'RTL') → None

abstractmethod has_hdl_path(kind: str = '') → bool

abstractmethod get_hdl_path(paths: list[pyuvm._reg.uvm_reg_model.uvm_hdl_path_concat], kind: str = '') → None

abstractmethod get_full_hdl_path(paths: list[pyuvm._reg.uvm_reg_model.uvm_hdl_path_concat], kind: str = '', separator: str = '.') → None

abstractmethod get_hdl_path_kinds(kinds: list[str]) → None

abstractmethod async backdoor_read(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

abstractmethod async backdoor_write(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

abstractmethod backdoor_read_func(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → pyuvm._reg.uvm_reg_model.uvm_status_e

abstractmethod async pre_write(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

abstractmethod async post_write(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

abstractmethod async pre_read(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

abstractmethod async post_read(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

abstractmethod build_coverage(models: pyuvm._reg.uvm_reg_model.uvm_reg_cvr_t) → pyuvm._reg.uvm_reg_model.uvm_reg_cvr_t

abstractmethod add_coverage(models: pyuvm._reg.uvm_reg_model.uvm_reg_cvr_t) → None

abstractmethod set_coverage(is_on: pyuvm._reg.uvm_reg_model.uvm_reg_cvr_t) → pyuvm._reg.uvm_reg_model.uvm_reg_cvr_t

abstractmethod get_coverage(is_on: pyuvm._reg.uvm_reg_model.uvm_reg_cvr_t) → bool

abstractmethod sample(offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, is_read: bool, map: pyuvm._reg.uvm_reg_map.uvm_reg_map) → None

_sample(addr: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, is_read: bool, map: pyuvm._reg.uvm_reg_map.uvm_reg_map) → None