pyuvm._reg.uvm_reg_map

Module Contents

Classes

uvm_reg_map_info
uvm_reg_transaction_order_policy
uvm_reg_seq_base
uvm_reg_map

Functions

ceildiv

Ceils the division of a by b

Data

__all__
logger

API

pyuvm._reg.uvm_reg_map.__all__

[‘uvm_reg_map_info’, ‘uvm_reg_transaction_order_policy’, ‘uvm_reg_seq_base’, ‘uvm_reg_map’]

pyuvm._reg.uvm_reg_map.logger

‘getLogger(…)’

class pyuvm._reg.uvm_reg_map.uvm_reg_map_info

Initialization

class pyuvm._reg.uvm_reg_map.uvm_reg_transaction_order_policy(name: str = 'policy')

Bases: pyuvm._s05_base_classes.uvm_object

abstractmethod order(q: list[pyuvm._reg.uvm_reg_item.uvm_reg_bus_op]) → None

class pyuvm._reg.uvm_reg_map.uvm_reg_seq_base(name: str = 'uvm_reg_seq_base')

Bases: pyuvm._s14_15_python_sequences.uvm_sequence_base

class pyuvm._reg.uvm_reg_map.uvm_reg_map(name: str = 'uvm_reg_map')

Bases: pyuvm._s05_base_classes.uvm_object

_backdoor: ClassVar[pyuvm._reg.uvm_reg_backdoor.uvm_reg_backdoor | None]

None

_init_address_map() → None

static backdoor() → pyuvm._reg.uvm_reg_backdoor.uvm_reg_backdoor

configure(parent: pyuvm._reg.uvm_reg_block.uvm_reg_block, base_addr: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, n_bytes: int = None, endian: pyuvm._reg.uvm_reg_model.uvm_endianness_e = None, byte_addressing: bool = True) → None

add_reg(rg: pyuvm._reg.uvm_reg.uvm_reg, offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, rights: str = 'RW', unmapped: bool = False, frontdoor: pyuvm._reg.uvm_reg_sequence.uvm_reg_frontdoor = None) → None

abstractmethod add_mem(mem: pyuvm._reg.uvm_mem.uvm_mem, offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, rights: str = 'RW', unmapped: bool = False, frontdoor: pyuvm._reg.uvm_reg_sequence.uvm_reg_frontdoor = None)

add_submap(child_map: pyuvm._reg.uvm_reg_map.uvm_reg_map, offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t) → None

set_sequencer(sequencer: pyuvm.uvm_sequencer, adapter: pyuvm._reg.uvm_reg_adapter.uvm_reg_adapter = None) → None

set_submap_offset(submap: pyuvm._reg.uvm_reg_map.uvm_reg_map, offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t) → None

get_submap_offset(submap: pyuvm._reg.uvm_reg_map.uvm_reg_map) → pyuvm._reg.uvm_reg_model.uvm_reg_addr_t

abstractmethod set_base_addr(offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t) → None

reset(kind: str = 'SOFT') → None

_add_parent_map(parent_map: pyuvm._reg.uvm_reg_map.uvm_reg_map, offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t) → None

abstractmethod _verify_map_config() → None

_set_reg_offset(reg: pyuvm._reg.uvm_reg.uvm_reg, offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, unmapped: bool) → None

abstractmethod _set_mem_offset(mem: pyuvm._reg.uvm_mem.uvm_mem, offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, unmapped: bool) → None

get_full_name() → str

get_root_map() → pyuvm._reg.uvm_reg_map.uvm_reg_map

get_parent() → pyuvm._reg.uvm_reg_block.uvm_reg_block

get_parent_map() → pyuvm._reg.uvm_reg_map.uvm_reg_map

get_base_addr(hier: pyuvm._reg.uvm_reg_model.uvm_hier_e = uvm_hier_e.UVM_HIER) → pyuvm._reg.uvm_reg_model.uvm_reg_addr_t

get_n_bytes(hier: pyuvm._reg.uvm_reg_model.uvm_hier_e = uvm_hier_e.UVM_HIER) → int

get_addr_unit_bytes() → int

get_endian(hier: pyuvm._reg.uvm_reg_model.uvm_hier_e = uvm_hier_e.UVM_HIER) → pyuvm._reg.uvm_reg_model.uvm_endianness_e

get_sequencer(hier: pyuvm._reg.uvm_reg_model.uvm_hier_e = uvm_hier_e.UVM_HIER) → pyuvm.uvm_sequencer_base

get_adapter(hier: pyuvm._reg.uvm_reg_model.uvm_hier_e = uvm_hier_e.UVM_HIER) → pyuvm._reg.uvm_reg_adapter.uvm_reg_adapter

get_submaps(hier: pyuvm._reg.uvm_reg_model.uvm_hier_e = uvm_hier_e.UVM_HIER) → list[pyuvm._reg.uvm_reg_map.uvm_reg_map]

get_registers(hier: pyuvm._reg.uvm_reg_model.uvm_hier_e = uvm_hier_e.UVM_HIER) → list[pyuvm._reg.uvm_reg.uvm_reg]

get_fields(hier: pyuvm._reg.uvm_reg_model.uvm_hier_e = uvm_hier_e.UVM_HIER) → list[pyuvm._reg.uvm_reg_field.uvm_reg_field]

get_memories(hier: pyuvm._reg.uvm_reg_model.uvm_hier_e = uvm_hier_e.UVM_HIER) → list[pyuvm._reg.uvm_mem.uvm_mem]

get_virtual_registers(hier: pyuvm._reg.uvm_reg_model.uvm_hier_e = uvm_hier_e.UVM_HIER) → list[pyuvm._reg.uvm_vreg.uvm_vreg]

get_virtual_fields(hier: pyuvm._reg.uvm_reg_model.uvm_hier_e = uvm_hier_e.UVM_HIER) → list[pyuvm._reg.uvm_vreg_field.uvm_vreg_field]

get_reg_map_info(rg: pyuvm._reg.uvm_reg.uvm_reg, error: bool = True) → pyuvm._reg.uvm_reg_map.uvm_reg_map_info | None

abstractmethod get_mem_map_info(mem: pyuvm._reg.uvm_mem.uvm_mem, error: bool) → pyuvm._reg.uvm_reg_map.uvm_reg_map_info

abstractmethod get_size() → int

get_physical_addresses(base_addr: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, mem_offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, n_bytes: int) → tuple[int, list[pyuvm._reg.uvm_reg_model.uvm_reg_addr_t]]

get_reg_by_offset(offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, read: bool = True) → pyuvm._reg.uvm_reg.uvm_reg | None

abstractmethod get_mem_by_offset(offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t) → pyuvm._reg.uvm_mem.uvm_mem

set_auto_predict(on: bool = True) → None

get_auto_predict() → bool

set_check_on_read(on: bool = True) → None

get_check_on_read() → bool

async do_bus_write(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item, sequencer: pyuvm.uvm_sequencer_base, adapter: pyuvm._reg.uvm_reg_adapter.uvm_reg_adapter) → None

async do_bus_read(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item, sequencer: pyuvm.uvm_sequencer_base, adapter: pyuvm._reg.uvm_reg_adapter.uvm_reg_adapter) → None

async do_write(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

async do_read(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → None

_get_bus_info(rw: pyuvm._reg.uvm_reg_item.uvm_reg_item) → tuple[pyuvm._reg.uvm_reg_map.uvm_reg_map_info, int, int, int]

set_transaction_order_policy(pol: pyuvm._reg.uvm_reg_map.uvm_reg_transaction_order_policy) → None

get_transaction_order_policy() → pyuvm._reg.uvm_reg_map.uvm_reg_transaction_order_policy

_get_physical_addresses_to_map(base_addr: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, mem_offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, n_bytes: int, parent_map: pyuvm._reg.uvm_reg_map.uvm_reg_map, mem: pyuvm._reg.uvm_mem.uvm_mem = None) → tuple[int, list[pyuvm._reg.uvm_reg_model.uvm_reg_addr_t], int]

abstractmethod async perform_accesses(accesses: list[pyuvm._reg.uvm_reg_item.uvm_reg_bus_op], rw: pyuvm._reg.uvm_reg_item.uvm_reg_item, adapter: pyuvm._reg.uvm_reg_adapter.uvm_reg_adapter, sequencer: pyuvm.uvm_sequencer_base) → None

abstractmethod unregister() → None

abstractmethod clone_and_update(rights: str) → pyuvm._reg.uvm_reg_map.uvm_reg_map

get_offset() → pyuvm._reg.uvm_reg_model.uvm_reg_addr_t

set_adapter(adapter) → None

pyuvm._reg.uvm_reg_map.ceildiv(a: int, b: int) → int

Ceils the division of a by b