pyuvm._reg.uvm_reg_block

Module Contents

Classes

uvm_reg_block

Data

__all__
logger

API

pyuvm._reg.uvm_reg_block.__all__

[‘uvm_reg_block’]

pyuvm._reg.uvm_reg_block.logger

‘getLogger(…)’

class pyuvm._reg.uvm_reg_block.uvm_reg_block(name: str = '', has_coverage: int = uvm_coverage_model_e.UVM_NO_COVERAGE)

Bases: pyuvm._s05_base_classes.uvm_object

_root_names: ClassVar[list[str]]

‘list(…)’

_roots: ClassVar[list[pyuvm._reg.uvm_reg_block.uvm_reg_block]]

‘list(…)’

_enable_reg_lookup_cache: ClassVar[bool]

False

_reg_block_registry: ClassVar[dict[str, pyuvm._reg.uvm_reg_block.uvm_reg_block]]

‘dict(…)’

configure(parent: pyuvm._reg.uvm_reg_block.uvm_reg_block = None, hdl_path: str = '') → None

create_map(name: str, base_addr: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, n_bytes: int, endian: pyuvm._reg.uvm_reg_model.uvm_endianness_e, byte_addressing: bool = True) → pyuvm._reg.uvm_reg_map.uvm_reg_map

abstractmethod static check_data_width(width: int) → bool

set_default_map(map: pyuvm._reg.uvm_reg_map.uvm_reg_map) → None

get_default_map() → pyuvm._reg.uvm_reg_map.uvm_reg_map

set_parent(parent: pyuvm._reg.uvm_reg_block.uvm_reg_block) → None

_add_block(blk: pyuvm._reg.uvm_reg_block.uvm_reg_block) → None

_add_map(map: pyuvm._reg.uvm_reg_map.uvm_reg_map) → None

_add_register(reg: pyuvm._reg.uvm_reg.uvm_reg) → None

abstractmethod _add_virtual_register(vreg: pyuvm._reg.uvm_vreg.uvm_vreg) → None

lock_model() → None

abstractmethod unlock_model() → None

async wait_for_lock() → None

is_locked() → bool

get_full_name() → str

get_parent() → pyuvm._reg.uvm_reg_block.uvm_reg_block

abstractmethod static get_root_blocks() → list[pyuvm._reg.uvm_reg_block.uvm_reg_block]

abstractmethod static find_blocks(name: str, root: pyuvm._reg.uvm_reg_block.uvm_reg_block = None, accessor: pyuvm._s05_base_classes.uvm_object = None) → list[pyuvm._reg.uvm_reg_block.uvm_reg_block]

get_blocks(hier: pyuvm._reg.uvm_reg_model.uvm_hier_e = uvm_hier_e.UVM_HIER) → list[pyuvm._reg.uvm_reg_block.uvm_reg_block]

get_maps() → list[pyuvm._reg.uvm_reg_map.uvm_reg_map]

get_registers(hier: pyuvm._reg.uvm_reg_model.uvm_hier_e = uvm_hier_e.UVM_HIER) → list[pyuvm._reg.uvm_reg.uvm_reg]

get_fields(hier: pyuvm._reg.uvm_reg_model.uvm_hier_e = uvm_hier_e.UVM_HIER) → list[pyuvm._reg.uvm_reg_field.uvm_reg_field]

get_memories(hier: pyuvm._reg.uvm_reg_model.uvm_hier_e = uvm_hier_e.UVM_HIER) → list[pyuvm._reg.uvm_mem.uvm_mem]

get_virtual_registers(hier: pyuvm._reg.uvm_reg_model.uvm_hier_e = uvm_hier_e.UVM_HIER) → list[pyuvm._reg.uvm_vreg.uvm_vreg]

get_virtual_fields(hier: pyuvm._reg.uvm_reg_model.uvm_hier_e = uvm_hier_e.UVM_HIER) → list[pyuvm._reg.uvm_vreg_field.uvm_vreg_field]

get_block_by_name(name: str) → pyuvm._reg.uvm_reg_block.uvm_reg_block | None

static get_block_by_full_name(name: str) → pyuvm._reg.uvm_reg_block.uvm_reg_block | None

get_map_by_name(name: str) → pyuvm._reg.uvm_reg_map.uvm_reg_map

get_reg_by_name(name: str) → pyuvm._reg.uvm_reg.uvm_reg | None

get_field_by_name(name: str) → pyuvm._reg.uvm_reg_field.uvm_reg_field

get_mem_by_name(name: str) → pyuvm._reg.uvm_mem.uvm_mem | None

get_vreg_by_name(name: str) → pyuvm._reg.uvm_vreg.uvm_vreg | None

get_vfield_by_name(name: str) → pyuvm._reg.uvm_vreg_field.uvm_vreg_field

abstractmethod build_coverage(models: pyuvm._reg.uvm_reg_model.uvm_reg_cvr_t) → pyuvm._reg.uvm_reg_model.uvm_reg_cvr_t

abstractmethod add_coverage(models: pyuvm._reg.uvm_reg_model.uvm_reg_cvr_t) → None

abstractmethod has_coverage(models: pyuvm._reg.uvm_reg_model.uvm_reg_cvr_t) → bool

abstractmethod set_coverage(is_on: pyuvm._reg.uvm_reg_model.uvm_reg_cvr_t) → pyuvm._reg.uvm_reg_model.uvm_reg_cvr_t

abstractmethod get_coverage(is_on: pyuvm._reg.uvm_reg_model.uvm_reg_cvr_t = uvm_coverage_model_e.UVM_CVR_ALL) → bool

abstractmethod sample(offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, is_read: bool, map: pyuvm._reg.uvm_reg_map.uvm_reg_map) → None

abstractmethod sample_values() → None

abstractmethod _sample(addr: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, is_read: bool, map: pyuvm._reg.uvm_reg_map.uvm_reg_map) → None

get_default_door() → pyuvm._reg.uvm_reg_model.uvm_door_e

set_default_door(door: pyuvm._reg.uvm_reg_model.uvm_door_e) → None

get_default_path() → pyuvm._reg.uvm_reg_model.uvm_path_e

reset(kind: str = 'HARD') → None

abstractmethod needs_update() → bool

abstractmethod async update(path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_DEFAULT_DOOR, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, prior: int = -1, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → pyuvm._reg.uvm_reg_model.uvm_status_e

abstractmethod async mirror(check: pyuvm._reg.uvm_reg_model.uvm_check_e = uvm_check_e.UVM_NO_CHECK, path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_DEFAULT_DOOR, parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, prior: int = -1, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → pyuvm._reg.uvm_reg_model.uvm_status_e

abstractmethod async write_reg_by_name(name: str, data: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_DEFAULT_DOOR, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, prior: int = -1, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → pyuvm._reg.uvm_reg_model.uvm_status_e

abstractmethod async read_reg_by_name(name: str, path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_DEFAULT_DOOR, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, prior: int = -1, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → tuple[pyuvm._reg.uvm_reg_model.uvm_status_e, pyuvm._reg.uvm_reg_model.uvm_reg_data_t]

abstractmethod async write_mem_by_name(name: str, offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, data: pyuvm._reg.uvm_reg_model.uvm_reg_data_t, path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_DEFAULT_DOOR, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, prior: int = -1, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → pyuvm._reg.uvm_reg_model.uvm_status_e

abstractmethod async read_mem_by_name(name: str, offset: pyuvm._reg.uvm_reg_model.uvm_reg_addr_t, path: pyuvm._reg.uvm_reg_model.uvm_door_e = uvm_door_e.UVM_DEFAULT_DOOR, map: pyuvm._reg.uvm_reg_map.uvm_reg_map = None, parent: pyuvm._s14_15_python_sequences.uvm_sequence_base = None, prior: int = -1, extension: pyuvm._s05_base_classes.uvm_object = None, fname: str = '', lineno: int = 0) → tuple[pyuvm._reg.uvm_reg_model.uvm_status_e, pyuvm._reg.uvm_reg_model.uvm_reg_data_t]

abstractmethod async readmemh() → None

abstractmethod async writememh() → None

abstractmethod get_backdoor(inherited: bool = True) → pyuvm._reg.uvm_reg_backdoor.uvm_reg_backdoor

abstractmethod set_backdoor(bkdr: pyuvm._reg.uvm_reg_backdoor.uvm_reg_backdoor, fname: str = '', lineno: int = 0) → None

abstractmethod clear_hdl_path(kind: str = 'RTL') → None

add_hdl_path(path: str, kind: str = 'RTL') → None

abstractmethod has_hdl_path(kind: str = '') → bool

abstractmethod get_hdl_path(paths: list[str], kind: str = '') → None

abstractmethod get_full_hdl_path(paths: list[str], kind: str = '', separator: str = '.') → None

abstractmethod set_default_hdl_path(kind: str) → None

abstractmethod get_default_hdl_path() → str

abstractmethod set_hdl_path_root(path: str, kind: str = 'RTL') → None

abstractmethod is_hdl_path_root(kind: str = '') → bool

_init_address_maps() → None

set_lock(v: bool = None) → None

abstractmethod _unregister(m: pyuvm._reg.uvm_reg_map.uvm_reg_map) → None

add_block(blk: pyuvm._reg.uvm_reg_block.uvm_reg_block) → None